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drm/amdgpu: add vcn_v5_0 ip dump support
Add support of vcn ip dump in the devcoredump for vcn_v5_0. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sunil Khatri
Alex Deucher
parent
947c080869
commit
a46a7bef7d
@ -37,6 +37,134 @@
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#include <drm/drm_drv.h>
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static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = {
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_CONFIG),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_STATUS),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
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SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
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};
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static int amdgpu_ih_clientid_vcns[] = {
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SOC15_IH_CLIENTID_VCN,
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SOC15_IH_CLIENTID_VCN1
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@ -83,6 +211,8 @@ static int vcn_v5_0_0_sw_init(void *handle)
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struct amdgpu_ring *ring;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int i, r;
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uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
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uint32_t *ptr;
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r = amdgpu_vcn_sw_init(adev);
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if (r)
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@ -137,6 +267,14 @@ static int vcn_v5_0_0_sw_init(void *handle)
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
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/* Allocate memory for VCN IP Dump buffer */
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ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
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if (!ptr) {
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DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
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adev->vcn.ip_dump = NULL;
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} else {
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adev->vcn.ip_dump = ptr;
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}
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return 0;
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}
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@ -173,6 +311,8 @@ static int vcn_v5_0_0_sw_fini(void *handle)
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r = amdgpu_vcn_sw_fini(adev);
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kfree(adev->vcn.ip_dump);
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return r;
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}
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@ -1297,6 +1437,34 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
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}
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}
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static void vcn_v5_0_dump_ip_state(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int i, j;
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bool is_powered;
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uint32_t inst_off;
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uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
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if (!adev->vcn.ip_dump)
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return;
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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inst_off = i * reg_count;
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/* mmUVD_POWER_STATUS is always readable and is first element of the array */
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adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
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is_powered = (adev->vcn.ip_dump[inst_off] &
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
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if (is_powered)
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for (j = 1; j < reg_count; j++)
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adev->vcn.ip_dump[inst_off + j] =
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RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
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}
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}
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static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
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.name = "vcn_v5_0_0",
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.early_init = vcn_v5_0_0_early_init,
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@ -1315,7 +1483,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
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.post_soft_reset = NULL,
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.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
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.set_powergating_state = vcn_v5_0_0_set_powergating_state,
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.dump_ip_state = NULL,
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.dump_ip_state = vcn_v5_0_dump_ip_state,
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.print_ip_state = NULL,
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};
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