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accel/ivpu: Fix sporadic VPU boot failure
Wait for AON bit in HOST_SS_CPR_RST_CLR to return 0 before
starting VPUIP power up sequence, otherwise the VPU device
may sporadically fail to boot.
An error in power up sequence is propagated to the runtime
power management - the device will be in an error state
until the VPU driver is reloaded.
Fixes: 35b137630f
("accel/ivpu: Introduce a new DRM driver for Intel VPU")
Cc: stable@vger.kernel.org # 6.3.x
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
Reviewed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230607094502.388489-1-stanislaw.gruszka@linux.intel.com
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@ -197,6 +197,11 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
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hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
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}
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static int ivpu_hw_mtl_wait_for_vpuip_bar(struct ivpu_device *vdev)
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{
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return REGV_POLL_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, AON, 0, 100);
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}
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static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
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{
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struct ivpu_hw_info *hw = vdev->hw;
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@ -239,6 +244,12 @@ static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
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ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
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return ret;
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}
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ret = ivpu_hw_mtl_wait_for_vpuip_bar(vdev);
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if (ret) {
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ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");
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return ret;
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}
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}
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return 0;
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@ -256,7 +267,7 @@ static int ivpu_pll_disable(struct ivpu_device *vdev)
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static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)
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{
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u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR);
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u32 val = 0;
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val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
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val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
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@ -91,6 +91,7 @@
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#define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK BIT_MASK(11)
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#define MTL_VPU_HOST_SS_CPR_RST_CLR 0x00000098u
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#define MTL_VPU_HOST_SS_CPR_RST_CLR_AON_MASK BIT_MASK(0)
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#define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK BIT_MASK(1)
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#define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK BIT_MASK(10)
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#define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK BIT_MASK(11)
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