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Merge branch 'stericsson/fixes' into next/cleanup
Conflicts: arch/arm/mach-ux500/cpu.c
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commit
a3849a4c03
@ -6,6 +6,7 @@ config UX500_SOC_COMMON
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select ARM_GIC
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select HAS_MTU
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select ARM_ERRATA_753970
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select ARM_ERRATA_754322
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menu "Ux500 SoC"
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@ -50,7 +50,27 @@ static void ux500_l2x0_inv_all(void)
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ux500_cache_sync();
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}
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static int ux500_l2x0_init(void)
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static int __init ux500_l2x0_unlock(void)
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{
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int i;
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/*
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* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
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* apparently locks both caches before jumping to the kernel. The
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* l2x0 core will not touch the unlock registers if the l2x0 is
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* already enabled, so we do it right here instead. The PL310 has
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* 8 sets of registers, one per possible CPU.
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*/
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for (i = 0; i < 8; i++) {
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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}
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return 0;
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}
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static int __init ux500_l2x0_init(void)
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{
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if (cpu_is_u5500())
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l2x0_base = __io_address(U5500_L2CC_BASE);
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@ -59,6 +79,9 @@ static int ux500_l2x0_init(void)
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else
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ux500_unknown_soc();
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/* Unlock before init */
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ux500_l2x0_unlock();
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/* 64KB way size, 8 way associativity, force WA */
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l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
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