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MIPS: OCTEON: Enable use of FPU
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
dadaa1c2c0
commit
a36d8225bc
@ -22,7 +22,6 @@
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 0
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#define cpu_has_tx39_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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@ -41,7 +41,7 @@ obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
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obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
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obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
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obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SMP_UP) += smp-up.o
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@ -562,7 +562,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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case cop1_op:
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preempt_disable();
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if (is_fpu_owner())
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asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
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asm volatile(
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".set push\n"
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"\t.set mips1\n"
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"\tcfc1\t%0,$31\n"
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"\t.set pop" : "=r" (fcr31));
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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@ -10,24 +10,12 @@
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* written by Carsten Langgaard, carstenl@mips.com
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*/
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#include <asm/asm.h>
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#include <asm/cachectl.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-bits.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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#include <asm/asmmacro.h>
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/*
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* Offset to the current process status flags, the first 32 bytes of the
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* stack are not used.
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*/
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#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
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#define USE_ALTERNATE_RESUME_IMPL 1
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.set push
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.set arch=mips64r2
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#include "r4k_switch.S"
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.set pop
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/*
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* task_struct *resume(task_struct *prev, task_struct *next,
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* struct thread_info *next_ti, int usedfpu)
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@ -40,6 +28,61 @@
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cpu_save_nonscratch a0
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LONG_S ra, THREAD_REG31(a0)
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/*
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* check if we need to save FPU registers
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*/
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PTR_L t3, TASK_THREAD_INFO(a0)
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LONG_L t0, TI_FLAGS(t3)
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li t1, _TIF_USEDFPU
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and t2, t0, t1
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beqz t2, 1f
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nor t1, zero, t1
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and t0, t0, t1
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LONG_S t0, TI_FLAGS(t3)
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/*
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* clear saved user stack CU1 bit
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*/
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LONG_L t0, ST_OFF(t3)
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li t1, ~ST0_CU1
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and t0, t0, t1
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LONG_S t0, ST_OFF(t3)
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.set push
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.set arch=mips64r2
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fpu_save_double a0 t0 t1 # c0_status passed in t0
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# clobbers t1
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.set pop
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1:
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/* check if we need to save COP2 registers */
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PTR_L t2, TASK_THREAD_INFO(a0)
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LONG_L t0, ST_OFF(t2)
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bbit0 t0, 30, 1f
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/* Disable COP2 in the stored process state */
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li t1, ST0_CU2
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xor t0, t1
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LONG_S t0, ST_OFF(t2)
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/* Enable COP2 so we can save it */
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mfc0 t0, CP0_STATUS
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or t0, t1
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mtc0 t0, CP0_STATUS
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/* Save COP2 */
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daddu a0, THREAD_CP2
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jal octeon_cop2_save
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dsubu a0, THREAD_CP2
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/* Disable COP2 now that we are done */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU2
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xor t0, t1
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mtc0 t0, CP0_STATUS
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1:
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#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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/* Check if we need to store CVMSEG state */
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mfc0 t0, $11,7 /* CvmMemCtl */
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@ -85,12 +128,7 @@
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move $28, a2
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cpu_restore_nonscratch a1
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#if (_THREAD_SIZE - 32) < 0x8000
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PTR_ADDIU t0, $28, _THREAD_SIZE - 32
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#else
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PTR_LI t0, _THREAD_SIZE - 32
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PTR_ADDU t0, $28
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#endif
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PTR_ADDU t0, $28, _THREAD_SIZE - 32
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set_saved_sp t0, t1, t2
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mfc0 t1, CP0_STATUS /* Do we really need this? */
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@ -28,6 +28,7 @@
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*/
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#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
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#ifndef USE_ALTERNATE_RESUME_IMPL
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/*
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* task_struct *resume(task_struct *prev, task_struct *next,
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* struct thread_info *next_ti, s32 fp_save)
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@ -99,6 +100,8 @@
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jr ra
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END(resume)
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#endif /* USE_ALTERNATE_RESUME_IMPL */
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/*
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* Save a thread's fp context.
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*/
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@ -584,7 +584,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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if (insn.i_format.rs == bc_op) {
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preempt_disable();
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if (is_fpu_owner())
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asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
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asm volatile(
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".set push\n"
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"\t.set mips1\n"
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"\tcfc1\t%0,$31\n"
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"\t.set pop" : "=r" (fcr31));
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else
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fcr31 = current->thread.fpu.fcr31;
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preempt_enable();
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