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i.MX8MQ device tree support for 4.21:
- It contains the initial device tree support for i.MX8MQ - the first
ARM64 i.MX processor. It features a quad Cortex-A53 core that
operates at speeds of up to 1.3 GHz, a Cortex-M4 core for
low-power processing, a DRAM controller that supports 32-bit/16-bit
LPDDR4/DDR4/DDR3L memory, and hardware acceleration for 4K video
playback.
- A couple of patches from Baruch that add watchdog device for i.MX8MQ
enable it for imx8mq-evk board.
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Merge tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late
i.MX8MQ device tree support for 4.21:
- It contains the initial device tree support for i.MX8MQ - the first
ARM64 i.MX processor. It features a quad Cortex-A53 core that
operates at speeds of up to 1.3 GHz, a Cortex-M4 core for
low-power processing, a DRAM controller that supports 32-bit/16-bit
LPDDR4/DDR4/DDR3L memory, and hardware acceleration for 4K video
playback.
- A couple of patches from Baruch that add watchdog device for i.MX8MQ
enable it for imx8mq-evk board.
* tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq-evk: enable watchdog
arm64: dts: imx8mq: add watchdog devices
MAINTAINERS: add i.MX8 DT path to i.MX architecture
arm64: add support for i.MX8M EVK board
arm64: add basic DTS for i.MX8MQ
arm64: add basic Kconfig symbols for i.MX8
arm64: dts: ls1046a: add qdma device tree nodes
arm64: dts: ls1043a: add qdma device tree nodes
arm64: dts: ls1088a: Add missing dma-ranges property
arm64: dts: ls1088a: Move fsl-mc node
arm64: dts: fsl: Add all CPUs in cooling maps
arm64: dts: Add support for NXP LS1028A SoC
arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
arm64: dts: fsl: Add the status property disable PCIe
arm64: dts: ls1012a: Add FRWY-LS1012A board support
dt-bindings: Add binding for i.MX8MQ CCM
arm64: dts: add LX2160AQDS board support
arm64: dts: add LX2160ARDB board support
arm64: dts: add QorIQ LX2160A SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a2edaf7893
20
Documentation/devicetree/bindings/clock/imx8mq-clock.txt
Normal file
20
Documentation/devicetree/bindings/clock/imx8mq-clock.txt
Normal file
@ -0,0 +1,20 @@
|
||||
* Clock bindings for NXP i.MX8M Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mq-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "ckil"
|
||||
- "osc_25m"
|
||||
- "osc_27m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
@ -1523,6 +1523,7 @@ F: arch/arm/mach-imx/
|
||||
F: arch/arm/mach-mxs/
|
||||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
F: arch/arm64/boot/dts/freescale/imx*
|
||||
F: drivers/clk/imx/
|
||||
F: drivers/firmware/imx/
|
||||
F: drivers/soc/imx/
|
||||
|
||||
@ -142,6 +142,14 @@ config ARCH_MVEBU
|
||||
- Armada 7K SoC Family
|
||||
- Armada 8K SoC Family
|
||||
|
||||
config ARCH_MXC
|
||||
bool "ARMv8 based NXP i.MX SoC family"
|
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select ARM64_ERRATUM_843419
|
||||
select ARM64_ERRATUM_845719
|
||||
help
|
||||
This enables support for the ARMv8 based SoCs in the
|
||||
NXP i.MX family.
|
||||
|
||||
config ARCH_QCOM
|
||||
bool "Qualcomm Platforms"
|
||||
select GPIOLIB
|
||||
|
||||
@ -1,7 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
|
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
|
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
|
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
|
||||
@ -13,3 +16,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
|
||||
|
||||
25
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
Normal file
25
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
Normal file
@ -0,0 +1,25 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for Freescale LS1012A FRWY Board.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Pramod Kumar <pramod.kumar_1@nxp.com>
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-ls1012a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1012A FRWY Board";
|
||||
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -475,7 +475,7 @@
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1012a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -496,6 +496,7 @@
|
||||
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
93
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
Normal file
93
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
Normal file
@ -0,0 +1,93 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for NXP LS1028A QDS Board.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Harninder Rai <harninder.rai@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-ls1028a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1028A QDS Board";
|
||||
compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9847";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
current-monitor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
current-monitor@41 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
73
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
Normal file
73
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
Normal file
@ -0,0 +1,73 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for NXP LS1028A RDB Board.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Harninder Rai <harninder.rai@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "fsl-ls1028a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1028A RDB Board";
|
||||
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
|
||||
|
||||
aliases {
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x0000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9847";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x02>;
|
||||
|
||||
current-monitor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <500>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
339
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
Normal file
339
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
Normal file
@ -0,0 +1,339 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for NXP Layerscape-1028A family SoC.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Harninder Rai <harninder.rai@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1028a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x00010000>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: clock-sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@6000000 {
|
||||
compatible= "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
|
||||
#interrupt-cells= <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
its: gic-its@6020000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
dcfg: syscon@1e00000 {
|
||||
compatible = "fsl,ls1028a-dcfg", "syscon";
|
||||
reg = <0x0 0x1e00000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
scfg: syscon@1fc0000 {
|
||||
compatible = "fsl,ls1028a-scfg", "syscon";
|
||||
reg = <0x0 0x1fc0000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clock-controller@1300000 {
|
||||
compatible = "fsl,ls1028a-clockgen";
|
||||
reg = <0x0 0x1300000 0x0 0xa0000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@2000000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2010000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2010000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@2020000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2020000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@2030000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@2040000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2040000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@2050000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2050000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@2060000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2060000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@2070000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2070000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
wdog0: watchdog@23c0000 {
|
||||
compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x0 0x23c0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1028a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu: iommu@5000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0 0x5000000 0 0x800000>;
|
||||
#global-interrupts = <8>;
|
||||
#iommu-cells = <1>;
|
||||
stream-match-mask = <0x7c00>;
|
||||
/* global secure fault */
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
/* combined secure interrupt */
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
/* global non-secure fault */
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
/* combined non-secure interrupt */
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
/* performance counter interrupts 0-7 */
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
/* per context interrupt, 64 interrupts */
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -171,8 +171,10 @@
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -661,7 +663,7 @@
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1043a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -683,10 +685,11 @@
|
||||
<0000 0 0 2 &gic 0 111 0x4>,
|
||||
<0000 0 0 3 &gic 0 112 0x4>,
|
||||
<0000 0 0 4 &gic 0 113 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1043a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -708,10 +711,11 @@
|
||||
<0000 0 0 2 &gic 0 121 0x4>,
|
||||
<0000 0 0 3 &gic 0 122 0x4>,
|
||||
<0000 0 0 4 &gic 0 123 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1043a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -733,7 +737,30 @@
|
||||
<0000 0 0 2 &gic 0 155 0x4>,
|
||||
<0000 0 0 3 &gic 0 156 0x4>,
|
||||
<0000 0 0 4 &gic 0 157 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdma: dma-controller@8380000 {
|
||||
compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
dma-channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
fsl,dma-queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
||||
@ -140,8 +140,10 @@
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -630,7 +632,7 @@
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1046a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -652,10 +654,11 @@
|
||||
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1046a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -677,10 +680,11 @@
|
||||
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1046a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -702,6 +706,28 @@
|
||||
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdma: dma-controller@8380000 {
|
||||
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
dma-channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
fsl,dma-queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@ -152,15 +152,14 @@
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu4 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -174,77 +173,6 @@
|
||||
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
|
||||
};
|
||||
|
||||
fsl_mc: fsl-mc@80c000000 {
|
||||
compatible = "fsl,qoriq-mc";
|
||||
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
||||
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
||||
msi-parent = <&its>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Region type 0x0 - MC portals
|
||||
* Region type 0x1 - QBMAN portals
|
||||
*/
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
||||
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
||||
|
||||
dpmacs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dpmac1: dpmac@1 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
dpmac2: dpmac@2 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
dpmac3: dpmac@3 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
dpmac4: dpmac@4 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
dpmac5: dpmac@5 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
dpmac6: dpmac@6 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
dpmac7: dpmac@7 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
dpmac8: dpmac@8 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
dpmac9: dpmac@9 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
dpmac10: dpmac@a {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
@ -262,6 +190,7 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
clockgen: clocking@1300000 {
|
||||
compatible = "fsl,ls1088a-clockgen";
|
||||
@ -512,7 +441,7 @@
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1088a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -533,10 +462,11 @@
|
||||
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1088a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -557,10 +487,11 @@
|
||||
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls1088a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x30 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
@ -581,6 +512,7 @@
|
||||
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cluster1_core0_watchdog: wdt@c000000 {
|
||||
@ -638,6 +570,77 @@
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
};
|
||||
|
||||
fsl_mc: fsl-mc@80c000000 {
|
||||
compatible = "fsl,qoriq-mc";
|
||||
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
||||
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
||||
msi-parent = <&its>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Region type 0x0 - MC portals
|
||||
* Region type 0x1 - QBMAN portals
|
||||
*/
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
||||
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
||||
|
||||
dpmacs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dpmac1: dpmac@1 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
dpmac2: dpmac@2 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
dpmac3: dpmac@3 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
dpmac4: dpmac@4 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
dpmac5: dpmac@5 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
dpmac6: dpmac@6 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
dpmac7: dpmac@7 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
dpmac8: dpmac@8 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
dpmac9: dpmac@9 {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
dpmac10: dpmac@a {
|
||||
compatible = "fsl,qoriq-mc-dpmac";
|
||||
reg = <0xa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
||||
@ -119,7 +119,7 @@
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls2088a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
|
||||
@ -128,7 +128,7 @@
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls2088a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
|
||||
@ -137,7 +137,7 @@
|
||||
};
|
||||
|
||||
&pcie3 {
|
||||
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls2088a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x30 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
|
||||
@ -146,7 +146,7 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
|
||||
compatible = "fsl,ls2088a-pcie";
|
||||
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
||||
0x38 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
|
||||
|
||||
@ -101,26 +101,14 @@
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map2 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu4 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map3 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu6 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -630,8 +618,7 @@
|
||||
};
|
||||
|
||||
pcie1: pcie@3400000 {
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
||||
"snps,dw-pcie";
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 108 0x4>; /* Level high type */
|
||||
interrupt-names = "intr";
|
||||
@ -648,11 +635,11 @@
|
||||
<0000 0 0 2 &gic 0 0 0 110 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 111 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 112 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2: pcie@3500000 {
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
||||
"snps,dw-pcie";
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 113 0x4>; /* Level high type */
|
||||
interrupt-names = "intr";
|
||||
@ -669,11 +656,11 @@
|
||||
<0000 0 0 2 &gic 0 0 0 115 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 116 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 117 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3: pcie@3600000 {
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
||||
"snps,dw-pcie";
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 118 0x4>; /* Level high type */
|
||||
interrupt-names = "intr";
|
||||
@ -690,11 +677,11 @@
|
||||
<0000 0 0 2 &gic 0 0 0 120 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 121 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 122 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie4: pcie@3700000 {
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
|
||||
"snps,dw-pcie";
|
||||
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 123 0x4>; /* Level high type */
|
||||
interrupt-names = "intr";
|
||||
@ -711,6 +698,7 @@
|
||||
<0000 0 0 2 &gic 0 0 0 125 4>,
|
||||
<0000 0 0 3 &gic 0 0 0 126 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 127 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata0: sata@3200000 {
|
||||
|
||||
112
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
Normal file
112
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
Normal file
@ -0,0 +1,112 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
//
|
||||
// Device Tree file for LX2160AQDS
|
||||
//
|
||||
// Copyright 2018 NXP
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-lx2160a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP Layerscape LX2160AQDS";
|
||||
compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
sb_3v3: regulator-sb3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MC34717-3.3VSB";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
power-monitor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <500>;
|
||||
};
|
||||
|
||||
power-monitor@41 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "nxp,sa56004";
|
||||
reg = <0x4c>;
|
||||
vcc-supply = <&sb_3v3>;
|
||||
};
|
||||
|
||||
temperature-sensor@4d {
|
||||
compatible = "nxp,sa56004";
|
||||
reg = <0x4d>;
|
||||
vcc-supply = <&sb_3v3>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
119
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
Normal file
119
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
Normal file
@ -0,0 +1,119 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
//
|
||||
// Device Tree file for LX2160ARDB
|
||||
//
|
||||
// Copyright 2018 NXP
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-lx2160a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP Layerscape LX2160ARDB";
|
||||
compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
sb_3v3: regulator-sb3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MC34717-3.3VSB";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr12;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
power-monitor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "nxp,sa56004";
|
||||
reg = <0x4c>;
|
||||
vcc-supply = <&sb_3v3>;
|
||||
};
|
||||
|
||||
temperature-sensor@4d {
|
||||
compatible = "nxp,sa56004";
|
||||
reg = <0x4d>;
|
||||
vcc-supply = <&sb_3v3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
// IRQ10_B
|
||||
interrupts = <0 150 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
766
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Normal file
766
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Normal file
@ -0,0 +1,766 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
//
|
||||
// Device Tree Include file for Layerscape-LX2160A family SoC.
|
||||
//
|
||||
// Copyright 2018 NXP
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,lx2160a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
// 8 clusters having 2 Cortex-A72 cores each
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x100>;
|
||||
clocks = <&clockgen 1 1>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x101>;
|
||||
clocks = <&clockgen 1 1>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x200>;
|
||||
clocks = <&clockgen 1 2>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x201>;
|
||||
clocks = <&clockgen 1 2>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x300>;
|
||||
clocks = <&clockgen 1 3>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu@301 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x301>;
|
||||
clocks = <&clockgen 1 3>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x400>;
|
||||
clocks = <&clockgen 1 4>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster4_l2>;
|
||||
};
|
||||
|
||||
cpu@401 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x401>;
|
||||
clocks = <&clockgen 1 4>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster4_l2>;
|
||||
};
|
||||
|
||||
cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x500>;
|
||||
clocks = <&clockgen 1 5>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster5_l2>;
|
||||
};
|
||||
|
||||
cpu@501 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x501>;
|
||||
clocks = <&clockgen 1 5>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster5_l2>;
|
||||
};
|
||||
|
||||
cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x600>;
|
||||
clocks = <&clockgen 1 6>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster6_l2>;
|
||||
};
|
||||
|
||||
cpu@601 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x601>;
|
||||
clocks = <&clockgen 1 6>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster6_l2>;
|
||||
};
|
||||
|
||||
cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x700>;
|
||||
clocks = <&clockgen 1 7>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster7_l2>;
|
||||
};
|
||||
|
||||
cpu@701 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
enable-method = "psci";
|
||||
reg = <0x701>;
|
||||
clocks = <&clockgen 1 7>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <192>;
|
||||
next-level-cache = <&cluster7_l2>;
|
||||
};
|
||||
|
||||
cluster0_l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster1_l2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster2_l2: l2-cache2 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster3_l2: l2-cache3 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster4_l2: l2-cache4 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster5_l2: l2-cache5 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster6_l2: l2-cache6 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
cluster7_l2: l2-cache7 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@6000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
|
||||
<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
|
||||
// SGI_base)
|
||||
<0x0 0x0c0c0000 0 0x2000>, // GICC
|
||||
<0x0 0x0c0d0000 0 0x1000>, // GICH
|
||||
<0x0 0x0c0e0000 0 0x20000>; // GICV
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its: gic-its@6020000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0x6020000 0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
// DRAM space - 1, size : 2 GB DRAM
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@1090000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1090000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
// One clock unit-sysclk node which bootloader require during DT fix-up
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>; // fixed up by bootloader
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
crypto: crypto@8000000 {
|
||||
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x8000000 0x100000>;
|
||||
reg = <0x00 0x8000000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
clockgen: clock-controller@1300000 {
|
||||
compatible = "fsl,lx2160a-clockgen";
|
||||
reg = <0 0x1300000 0 0xa0000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
dcfg: syscon@1e00000 {
|
||||
compatible = "fsl,lx2160a-dcfg", "syscon";
|
||||
reg = <0x0 0x1e00000 0x0 0x10000>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
i2c0: i2c@2000000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2010000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2010000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@2020000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2020000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@2030000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2030000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@2040000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2040000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@2050000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2050000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@2060000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2060000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@2070000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2070000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc0: esdhc@2140000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x2140000 0x0 0x10000>;
|
||||
interrupts = <0 28 0x4>; /* Level high type */
|
||||
clocks = <&clockgen 4 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
little-endian;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc1: esdhc@2150000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x2150000 0x0 0x10000>;
|
||||
interrupts = <0 63 0x4>; /* Level high type */
|
||||
clocks = <&clockgen 4 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
broken-cd;
|
||||
little-endian;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@21c0000 {
|
||||
compatible = "arm,sbsa-uart","arm,pl011";
|
||||
reg = <0x0 0x21c0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@21d0000 {
|
||||
compatible = "arm,sbsa-uart","arm,pl011";
|
||||
reg = <0x0 0x21d0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@21e0000 {
|
||||
compatible = "arm,sbsa-uart","arm,pl011";
|
||||
reg = <0x0 0x21e0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@21f0000 {
|
||||
compatible = "arm,sbsa-uart","arm,pl011";
|
||||
reg = <0x0 0x21f0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
little-endian;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
little-endian;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
little-endian;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
little-endian;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
watchdog@23a0000 {
|
||||
compatible = "arm,sbsa-gwdt";
|
||||
reg = <0x0 0x23a0000 0 0x1000>,
|
||||
<0x0 0x2390000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-sec = <30>;
|
||||
};
|
||||
|
||||
usb0: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@3110000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3110000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu: iommu@5000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0 0x5000000 0 0x800000>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <14>;
|
||||
// global secure fault
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
// combined secure
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
// global non-secure fault
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
// combined non-secure
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
// performance counter interrupts 0-9
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
// per context interrupt, 64 interrupts
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
};
|
||||
303
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
Normal file
303
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
Normal file
@ -0,0 +1,303 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mq.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MQ EVK";
|
||||
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x8>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1675000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1625000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3625000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vqmmc-supply = <&sw4_reg>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2: regusdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
623
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
Normal file
623
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
Normal file
@ -0,0 +1,623 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX8MQ_PINFUNC_H
|
||||
#define __DTS_IMX8MQ_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
|
||||
|
||||
#endif /* __DTS_IMX8MQ_PINFUNC_H */
|
||||
416
arch/arm64/boot/dts/freescale/imx8mq.dtsi
Normal file
416
arch/arm64/boot/dts/freescale/imx8mq.dtsi
Normal file
@ -0,0 +1,416 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "imx8mq-pinfunc.h"
|
||||
|
||||
/ {
|
||||
/* This should really be the GPC, but we need a driver for this first */
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ckil: clock-ckil {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ckil";
|
||||
};
|
||||
|
||||
osc_25m: clock-osc-25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "osc_25m";
|
||||
};
|
||||
|
||||
osc_27m: clock-osc-27m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
clock-output-names = "osc_27m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
|
||||
interrupt-parent = <&gic>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
bus@30000000 { /* AIPS1 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
iomuxc_gpr: syscon@30340000 {
|
||||
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
anatop: syscon@30360000 {
|
||||
compatible = "fsl,imx8mq-anatop", "syscon";
|
||||
reg = <0x30360000 0x10000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
||||
<&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "ckil", "osc_25m", "osc_27m",
|
||||
"clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: watchdog@30290000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30290000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: watchdog@302a0000 {
|
||||
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
bus@30400000 { /* AIPS2 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
};
|
||||
|
||||
bus@30800000 { /* AIPS3 */
|
||||
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>;
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx8mq-uart",
|
||||
"fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
|
||||
<&clk IMX8MQ_CLK_UART4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mq-usdhc",
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@30b50000 {
|
||||
compatible = "fsl,imx8mq-usdhc",
|
||||
"fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF>,
|
||||
<&clk IMX8MQ_CLK_ENET_PHY_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>, /* GIC Dist */
|
||||
<0x38880000 0xc0000>, /* GICR */
|
||||
<0x31000000 0x2000>, /* GICC */
|
||||
<0x31010000 0x2000>, /* GICV */
|
||||
<0x31020000 0x2000>; /* GICH */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
395
include/dt-bindings/clock/imx8mq-clock.h
Normal file
395
include/dt-bindings/clock/imx8mq-clock.h
Normal file
@ -0,0 +1,395 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
|
||||
#define IMX8MQ_CLK_DUMMY 0
|
||||
#define IMX8MQ_CLK_32K 1
|
||||
#define IMX8MQ_CLK_25M 2
|
||||
#define IMX8MQ_CLK_27M 3
|
||||
#define IMX8MQ_CLK_EXT1 4
|
||||
#define IMX8MQ_CLK_EXT2 5
|
||||
#define IMX8MQ_CLK_EXT3 6
|
||||
#define IMX8MQ_CLK_EXT4 7
|
||||
|
||||
/* ANAMIX PLL clocks */
|
||||
/* FRAC PLLs */
|
||||
/* ARM PLL */
|
||||
#define IMX8MQ_ARM_PLL_REF_SEL 8
|
||||
#define IMX8MQ_ARM_PLL_REF_DIV 9
|
||||
#define IMX8MQ_ARM_PLL 10
|
||||
#define IMX8MQ_ARM_PLL_BYPASS 11
|
||||
#define IMX8MQ_ARM_PLL_OUT 12
|
||||
|
||||
/* GPU PLL */
|
||||
#define IMX8MQ_GPU_PLL_REF_SEL 13
|
||||
#define IMX8MQ_GPU_PLL_REF_DIV 14
|
||||
#define IMX8MQ_GPU_PLL 15
|
||||
#define IMX8MQ_GPU_PLL_BYPASS 16
|
||||
#define IMX8MQ_GPU_PLL_OUT 17
|
||||
|
||||
/* VPU PLL */
|
||||
#define IMX8MQ_VPU_PLL_REF_SEL 18
|
||||
#define IMX8MQ_VPU_PLL_REF_DIV 19
|
||||
#define IMX8MQ_VPU_PLL 20
|
||||
#define IMX8MQ_VPU_PLL_BYPASS 21
|
||||
#define IMX8MQ_VPU_PLL_OUT 22
|
||||
|
||||
/* AUDIO PLL1 */
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
|
||||
#define IMX8MQ_AUDIO_PLL1 25
|
||||
#define IMX8MQ_AUDIO_PLL1_BYPASS 26
|
||||
#define IMX8MQ_AUDIO_PLL1_OUT 27
|
||||
|
||||
/* AUDIO PLL2 */
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
|
||||
#define IMX8MQ_AUDIO_PLL2 30
|
||||
#define IMX8MQ_AUDIO_PLL2_BYPASS 31
|
||||
#define IMX8MQ_AUDIO_PLL2_OUT 32
|
||||
|
||||
/* VIDEO PLL1 */
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
|
||||
#define IMX8MQ_VIDEO_PLL1 35
|
||||
#define IMX8MQ_VIDEO_PLL1_BYPASS 36
|
||||
#define IMX8MQ_VIDEO_PLL1_OUT 37
|
||||
|
||||
/* SYS1 PLL */
|
||||
#define IMX8MQ_SYS1_PLL1_REF_SEL 38
|
||||
#define IMX8MQ_SYS1_PLL1_REF_DIV 39
|
||||
#define IMX8MQ_SYS1_PLL1 40
|
||||
#define IMX8MQ_SYS1_PLL1_OUT 41
|
||||
#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
|
||||
#define IMX8MQ_SYS1_PLL2 43
|
||||
#define IMX8MQ_SYS1_PLL2_DIV 44
|
||||
#define IMX8MQ_SYS1_PLL2_OUT 45
|
||||
|
||||
/* SYS2 PLL */
|
||||
#define IMX8MQ_SYS2_PLL1_REF_SEL 46
|
||||
#define IMX8MQ_SYS2_PLL1_REF_DIV 47
|
||||
#define IMX8MQ_SYS2_PLL1 48
|
||||
#define IMX8MQ_SYS2_PLL1_OUT 49
|
||||
#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
|
||||
#define IMX8MQ_SYS2_PLL2 51
|
||||
#define IMX8MQ_SYS2_PLL2_DIV 52
|
||||
#define IMX8MQ_SYS2_PLL2_OUT 53
|
||||
|
||||
/* SYS3 PLL */
|
||||
#define IMX8MQ_SYS3_PLL1_REF_SEL 54
|
||||
#define IMX8MQ_SYS3_PLL1_REF_DIV 55
|
||||
#define IMX8MQ_SYS3_PLL1 56
|
||||
#define IMX8MQ_SYS3_PLL1_OUT 57
|
||||
#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
|
||||
#define IMX8MQ_SYS3_PLL2 59
|
||||
#define IMX8MQ_SYS3_PLL2_DIV 60
|
||||
#define IMX8MQ_SYS3_PLL2_OUT 61
|
||||
|
||||
/* DRAM PLL */
|
||||
#define IMX8MQ_DRAM_PLL1_REF_SEL 62
|
||||
#define IMX8MQ_DRAM_PLL1_REF_DIV 63
|
||||
#define IMX8MQ_DRAM_PLL1 64
|
||||
#define IMX8MQ_DRAM_PLL1_OUT 65
|
||||
#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
|
||||
#define IMX8MQ_DRAM_PLL2 67
|
||||
#define IMX8MQ_DRAM_PLL2_DIV 68
|
||||
#define IMX8MQ_DRAM_PLL2_OUT 69
|
||||
|
||||
/* SYS PLL DIV */
|
||||
#define IMX8MQ_SYS1_PLL_40M 70
|
||||
#define IMX8MQ_SYS1_PLL_80M 71
|
||||
#define IMX8MQ_SYS1_PLL_100M 72
|
||||
#define IMX8MQ_SYS1_PLL_133M 73
|
||||
#define IMX8MQ_SYS1_PLL_160M 74
|
||||
#define IMX8MQ_SYS1_PLL_200M 75
|
||||
#define IMX8MQ_SYS1_PLL_266M 76
|
||||
#define IMX8MQ_SYS1_PLL_400M 77
|
||||
#define IMX8MQ_SYS1_PLL_800M 78
|
||||
|
||||
#define IMX8MQ_SYS2_PLL_50M 79
|
||||
#define IMX8MQ_SYS2_PLL_100M 80
|
||||
#define IMX8MQ_SYS2_PLL_125M 81
|
||||
#define IMX8MQ_SYS2_PLL_166M 82
|
||||
#define IMX8MQ_SYS2_PLL_200M 83
|
||||
#define IMX8MQ_SYS2_PLL_250M 84
|
||||
#define IMX8MQ_SYS2_PLL_333M 85
|
||||
#define IMX8MQ_SYS2_PLL_500M 86
|
||||
#define IMX8MQ_SYS2_PLL_1000M 87
|
||||
|
||||
/* CCM ROOT clocks */
|
||||
/* A53 */
|
||||
#define IMX8MQ_CLK_A53_SRC 88
|
||||
#define IMX8MQ_CLK_A53_CG 89
|
||||
#define IMX8MQ_CLK_A53_DIV 90
|
||||
/* M4 */
|
||||
#define IMX8MQ_CLK_M4_SRC 91
|
||||
#define IMX8MQ_CLK_M4_CG 92
|
||||
#define IMX8MQ_CLK_M4_DIV 93
|
||||
/* VPU */
|
||||
#define IMX8MQ_CLK_VPU_SRC 94
|
||||
#define IMX8MQ_CLK_VPU_CG 95
|
||||
#define IMX8MQ_CLK_VPU_DIV 96
|
||||
/* GPU CORE */
|
||||
#define IMX8MQ_CLK_GPU_CORE_SRC 97
|
||||
#define IMX8MQ_CLK_GPU_CORE_CG 98
|
||||
#define IMX8MQ_CLK_GPU_CORE_DIV 99
|
||||
/* GPU SHADER */
|
||||
#define IMX8MQ_CLK_GPU_SHADER_SRC 100
|
||||
#define IMX8MQ_CLK_GPU_SHADER_CG 101
|
||||
#define IMX8MQ_CLK_GPU_SHADER_DIV 102
|
||||
|
||||
/* BUS TYPE */
|
||||
/* MAIN AXI */
|
||||
#define IMX8MQ_CLK_MAIN_AXI 103
|
||||
/* ENET AXI */
|
||||
#define IMX8MQ_CLK_ENET_AXI 104
|
||||
/* NAND_USDHC_BUS */
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS 105
|
||||
/* VPU BUS */
|
||||
#define IMX8MQ_CLK_VPU_BUS 106
|
||||
/* DISP_AXI */
|
||||
#define IMX8MQ_CLK_DISP_AXI 107
|
||||
/* DISP APB */
|
||||
#define IMX8MQ_CLK_DISP_APB 108
|
||||
/* DISP RTRM */
|
||||
#define IMX8MQ_CLK_DISP_RTRM 109
|
||||
/* USB_BUS */
|
||||
#define IMX8MQ_CLK_USB_BUS 110
|
||||
/* GPU_AXI */
|
||||
#define IMX8MQ_CLK_GPU_AXI 111
|
||||
/* GPU_AHB */
|
||||
#define IMX8MQ_CLK_GPU_AHB 112
|
||||
/* NOC */
|
||||
#define IMX8MQ_CLK_NOC 113
|
||||
/* NOC_APB */
|
||||
#define IMX8MQ_CLK_NOC_APB 115
|
||||
|
||||
/* AHB */
|
||||
#define IMX8MQ_CLK_AHB 116
|
||||
/* AUDIO AHB */
|
||||
#define IMX8MQ_CLK_AUDIO_AHB 117
|
||||
|
||||
/* DRAM_ALT */
|
||||
#define IMX8MQ_CLK_DRAM_ALT 118
|
||||
/* DRAM APB */
|
||||
#define IMX8MQ_CLK_DRAM_APB 119
|
||||
/* VPU_G1 */
|
||||
#define IMX8MQ_CLK_VPU_G1 120
|
||||
/* VPU_G2 */
|
||||
#define IMX8MQ_CLK_VPU_G2 121
|
||||
/* DISP_DTRC */
|
||||
#define IMX8MQ_CLK_DISP_DTRC 122
|
||||
/* DISP_DC8000 */
|
||||
#define IMX8MQ_CLK_DISP_DC8000 123
|
||||
/* PCIE_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL 124
|
||||
/* PCIE_PHY */
|
||||
#define IMX8MQ_CLK_PCIE1_PHY 125
|
||||
/* PCIE_AUX */
|
||||
#define IMX8MQ_CLK_PCIE1_AUX 126
|
||||
/* DC_PIXEL */
|
||||
#define IMX8MQ_CLK_DC_PIXEL 127
|
||||
/* LCDIF_PIXEL */
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL 128
|
||||
/* SAI1~6 */
|
||||
#define IMX8MQ_CLK_SAI1 129
|
||||
|
||||
#define IMX8MQ_CLK_SAI2 130
|
||||
|
||||
#define IMX8MQ_CLK_SAI3 131
|
||||
|
||||
#define IMX8MQ_CLK_SAI4 132
|
||||
|
||||
#define IMX8MQ_CLK_SAI5 133
|
||||
|
||||
#define IMX8MQ_CLK_SAI6 134
|
||||
/* SPDIF1 */
|
||||
#define IMX8MQ_CLK_SPDIF1 135
|
||||
/* SPDIF2 */
|
||||
#define IMX8MQ_CLK_SPDIF2 136
|
||||
/* ENET_REF */
|
||||
#define IMX8MQ_CLK_ENET_REF 137
|
||||
/* ENET_TIMER */
|
||||
#define IMX8MQ_CLK_ENET_TIMER 138
|
||||
/* ENET_PHY */
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF 139
|
||||
/* NAND */
|
||||
#define IMX8MQ_CLK_NAND 140
|
||||
/* QSPI */
|
||||
#define IMX8MQ_CLK_QSPI 141
|
||||
/* USDHC1 */
|
||||
#define IMX8MQ_CLK_USDHC1 142
|
||||
/* USDHC2 */
|
||||
#define IMX8MQ_CLK_USDHC2 143
|
||||
/* I2C1 */
|
||||
#define IMX8MQ_CLK_I2C1 144
|
||||
/* I2C2 */
|
||||
#define IMX8MQ_CLK_I2C2 145
|
||||
/* I2C3 */
|
||||
#define IMX8MQ_CLK_I2C3 146
|
||||
/* I2C4 */
|
||||
#define IMX8MQ_CLK_I2C4 147
|
||||
/* UART1 */
|
||||
#define IMX8MQ_CLK_UART1 148
|
||||
/* UART2 */
|
||||
#define IMX8MQ_CLK_UART2 149
|
||||
/* UART3 */
|
||||
#define IMX8MQ_CLK_UART3 150
|
||||
/* UART4 */
|
||||
#define IMX8MQ_CLK_UART4 151
|
||||
/* USB_CORE_REF */
|
||||
#define IMX8MQ_CLK_USB_CORE_REF 152
|
||||
/* USB_PHY_REF */
|
||||
#define IMX8MQ_CLK_USB_PHY_REF 163
|
||||
/* ECSPI1 */
|
||||
#define IMX8MQ_CLK_ECSPI1 164
|
||||
/* ECSPI2 */
|
||||
#define IMX8MQ_CLK_ECSPI2 165
|
||||
/* PWM1 */
|
||||
#define IMX8MQ_CLK_PWM1 166
|
||||
/* PWM2 */
|
||||
#define IMX8MQ_CLK_PWM2 167
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||||
/* PWM3 */
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#define IMX8MQ_CLK_PWM3 168
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/* PWM4 */
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#define IMX8MQ_CLK_PWM4 169
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||||
/* GPT1 */
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||||
#define IMX8MQ_CLK_GPT1 170
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/* WDOG */
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#define IMX8MQ_CLK_WDOG 171
|
||||
/* WRCLK */
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||||
#define IMX8MQ_CLK_WRCLK 172
|
||||
/* DSI_CORE */
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#define IMX8MQ_CLK_DSI_CORE 173
|
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/* DSI_PHY */
|
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#define IMX8MQ_CLK_DSI_PHY_REF 174
|
||||
/* DSI_DBI */
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#define IMX8MQ_CLK_DSI_DBI 175
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/*DSI_ESC */
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#define IMX8MQ_CLK_DSI_ESC 176
|
||||
/* CSI1_CORE */
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||||
#define IMX8MQ_CLK_CSI1_CORE 177
|
||||
/* CSI1_PHY */
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF 178
|
||||
/* CSI_ESC */
|
||||
#define IMX8MQ_CLK_CSI1_ESC 179
|
||||
/* CSI2_CORE */
|
||||
#define IMX8MQ_CLK_CSI2_CORE 170
|
||||
/* CSI2_PHY */
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF 181
|
||||
/* CSI2_ESC */
|
||||
#define IMX8MQ_CLK_CSI2_ESC 182
|
||||
/* PCIE2_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL 183
|
||||
/* PCIE2_PHY */
|
||||
#define IMX8MQ_CLK_PCIE2_PHY 184
|
||||
/* PCIE2_AUX */
|
||||
#define IMX8MQ_CLK_PCIE2_AUX 185
|
||||
/* ECSPI3 */
|
||||
#define IMX8MQ_CLK_ECSPI3 186
|
||||
|
||||
/* CCGR clocks */
|
||||
#define IMX8MQ_CLK_A53_ROOT 187
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 188
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 189
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 180
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 181
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 182
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 193
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 194
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 195
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 196
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 197
|
||||
#define IMX8MQ_CLK_M4_ROOT 198
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 199
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 200
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 201
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 202
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 203
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 204
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 205
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 206
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 207
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 208
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 209
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 210
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 212
|
||||
#define IMX8MQ_CLK_UART1_ROOT 213
|
||||
#define IMX8MQ_CLK_UART2_ROOT 214
|
||||
#define IMX8MQ_CLK_UART3_ROOT 215
|
||||
#define IMX8MQ_CLK_UART4_ROOT 216
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 219
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 220
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 221
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 222
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 223
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 224
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 225
|
||||
#define IMX8MQ_CLK_GPU_ROOT 226
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 227
|
||||
#define IMX8MQ_CLK_AVC_ROOT 228
|
||||
#define IMX8MQ_CLK_VP9_ROOT 229
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
|
||||
#define IMX8MQ_CLK_DISP_ROOT 231
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 232
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 234
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 235
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 236
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 237
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 238
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 239
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 240
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 241
|
||||
|
||||
/* SCCG PLL GATE */
|
||||
#define IMX8MQ_SYS1_PLL_OUT 232
|
||||
#define IMX8MQ_SYS2_PLL_OUT 243
|
||||
#define IMX8MQ_SYS3_PLL_OUT 244
|
||||
#define IMX8MQ_DRAM_PLL_OUT 245
|
||||
|
||||
#define IMX8MQ_GPT_3M_CLK 246
|
||||
|
||||
#define IMX8MQ_CLK_IPG_ROOT 247
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
|
||||
#define IMX8MQ_CLK_SAI1_IPG 249
|
||||
#define IMX8MQ_CLK_SAI2_IPG 250
|
||||
#define IMX8MQ_CLK_SAI3_IPG 251
|
||||
#define IMX8MQ_CLK_SAI4_IPG 252
|
||||
#define IMX8MQ_CLK_SAI5_IPG 253
|
||||
#define IMX8MQ_CLK_SAI6_IPG 254
|
||||
|
||||
/* DSI AHB/IPG clocks */
|
||||
/* rxesc clock */
|
||||
#define IMX8MQ_CLK_DSI_AHB 255
|
||||
/* txesc clock */
|
||||
#define IMX8MQ_CLK_DSI_IPG_DIV 256
|
||||
|
||||
#define IMX8MQ_CLK_TMU_ROOT 265
|
||||
|
||||
/* Display root clocks */
|
||||
#define IMX8MQ_CLK_DISP_AXI_ROOT 266
|
||||
#define IMX8MQ_CLK_DISP_APB_ROOT 267
|
||||
#define IMX8MQ_CLK_DISP_RTRM_ROOT 268
|
||||
|
||||
#define IMX8MQ_CLK_OCOTP_ROOT 269
|
||||
|
||||
#define IMX8MQ_CLK_DRAM_ALT_ROOT 270
|
||||
#define IMX8MQ_CLK_DRAM_CORE 271
|
||||
|
||||
#define IMX8MQ_CLK_MU_ROOT 272
|
||||
#define IMX8MQ_VIDEO2_PLL_OUT 273
|
||||
|
||||
#define IMX8MQ_CLK_CLKO2 274
|
||||
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275
|
||||
|
||||
#define IMX8MQ_CLK_END 276
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
Loading…
Reference in New Issue
Block a user