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mv643xx_eth: remove port serial status register bit defines
All except one of the port serial status register bit defines are unused -- kill the unused ones. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Dale Farnsworth <dale@farnsworth.org>
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@ -103,6 +103,7 @@ static char mv643xx_driver_version[] = "1.0";
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#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
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#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
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#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
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#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
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#define PORT_STATUS(p) (0x0444 + ((p) << 10))
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#define PORT_STATUS(p) (0x0444 + ((p) << 10))
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#define TX_FIFO_EMPTY 0x00000400
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#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
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#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
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#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
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#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
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#define INT_CAUSE(p) (0x0460 + ((p) << 10))
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#define INT_CAUSE(p) (0x0460 + ((p) << 10))
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@ -169,18 +170,6 @@ static char mv643xx_driver_version[] = "1.0";
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#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
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#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
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#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
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#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
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/* Port serial status reg (PSR) */
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#define ETH_INTERFACE_PCM 0x00000001
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#define ETH_LINK_IS_UP 0x00000002
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#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
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#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
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#define ETH_GMII_SPEED_1000 0x00000010
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#define ETH_MII_SPEED_100 0x00000020
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#define ETH_TX_IN_PROGRESS 0x00000080
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#define ETH_BYPASS_ACTIVE 0x00000100
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#define ETH_PORT_AT_PARTITION_STATE 0x00000200
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#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
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/* SMI reg */
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/* SMI reg */
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#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
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#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
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#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
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#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
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@ -471,7 +460,7 @@ static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
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udelay(10);
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udelay(10);
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/* Wait for Tx FIFO to empty */
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/* Wait for Tx FIFO to empty */
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while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
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while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
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udelay(10);
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udelay(10);
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}
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}
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