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scsi: hisi_sas: add v3 code to send SSP frame
Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Xiang Chen
Martin K. Petersen
parent
60b4a5ee90
commit
a2204723ac
@ -157,6 +157,41 @@
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#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
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#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
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/* HW dma structures */
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/* Delivery queue header */
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/* dw0 */
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#define CMD_HDR_RESP_REPORT_OFF 5
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#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
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#define CMD_HDR_TLR_CTRL_OFF 6
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#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
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#define CMD_HDR_PORT_OFF 18
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#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
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#define CMD_HDR_PRIORITY_OFF 27
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#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
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#define CMD_HDR_CMD_OFF 29
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#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
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/* dw1 */
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#define CMD_HDR_DIR_OFF 5
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#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
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#define CMD_HDR_VDTL_OFF 10
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#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
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#define CMD_HDR_FRAME_TYPE_OFF 11
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#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
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#define CMD_HDR_DEV_ID_OFF 16
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#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
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/* dw2 */
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#define CMD_HDR_CFL_OFF 0
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#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
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#define CMD_HDR_MRFL_OFF 15
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#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
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#define CMD_HDR_SG_MOD_OFF 24
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#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
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/* dw6 */
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#define CMD_HDR_DIF_SGL_LEN_OFF 0
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#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
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#define CMD_HDR_DATA_SGL_LEN_OFF 16
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#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
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/* Completion header */
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/* dw0 */
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#define CMPLT_HDR_CMPLT_OFF 0
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@ -217,6 +252,11 @@ enum {
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HISI_SAS_PHY_INT_NR
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};
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#define DIR_NO_DATA 0
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#define DIR_TO_INI 1
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#define DIR_TO_DEVICE 2
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#define DIR_RESERVED 3
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static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
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{
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void __iomem *regs = hisi_hba->regs + off;
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@ -224,6 +264,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
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return readl(regs);
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}
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static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
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{
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void __iomem *regs = hisi_hba->regs + off;
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return readl_relaxed(regs);
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}
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static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
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{
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void __iomem *regs = hisi_hba->regs + off;
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@ -448,6 +495,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
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hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
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}
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/**
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* The callpath to this function and upto writing the write
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* queue pointer should be safe from interruption.
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*/
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static int
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get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
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{
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struct device *dev = hisi_hba->dev;
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int queue = dq->id;
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u32 r, w;
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w = dq->wr_point;
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r = hisi_sas_read32_relaxed(hisi_hba,
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DLVRY_Q_0_RD_PTR + (queue * 0x14));
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if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
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dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
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queue, r, w);
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return -EAGAIN;
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}
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return 0;
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}
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static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
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{
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struct hisi_hba *hisi_hba = dq->hisi_hba;
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int dlvry_queue = dq->slot_prep->dlvry_queue;
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int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
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dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
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hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
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dq->wr_point);
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}
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static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot,
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struct hisi_sas_cmd_hdr *hdr,
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struct scatterlist *scatter,
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int n_elem)
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{
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struct device *dev = hisi_hba->dev;
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struct scatterlist *sg;
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int i;
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if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
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dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
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n_elem);
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return -EINVAL;
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}
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slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
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&slot->sge_page_dma);
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if (!slot->sge_page)
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return -ENOMEM;
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for_each_sg(scatter, sg, n_elem, i) {
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struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
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entry->addr = cpu_to_le64(sg_dma_address(sg));
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entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
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entry->data_len = cpu_to_le32(sg_dma_len(sg));
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entry->data_off = 0;
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}
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hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
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hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
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return 0;
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}
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static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot, int is_tmf,
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struct hisi_sas_tmf_task *tmf)
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{
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struct sas_task *task = slot->task;
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struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
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struct domain_device *device = task->dev;
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struct hisi_sas_device *sas_dev = device->lldd_dev;
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struct hisi_sas_port *port = slot->port;
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struct sas_ssp_task *ssp_task = &task->ssp_task;
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struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
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int has_data = 0, rc, priority = is_tmf;
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u8 *buf_cmd;
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u32 dw1 = 0, dw2 = 0;
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hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
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(2 << CMD_HDR_TLR_CTRL_OFF) |
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(port->id << CMD_HDR_PORT_OFF) |
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(priority << CMD_HDR_PRIORITY_OFF) |
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(1 << CMD_HDR_CMD_OFF)); /* ssp */
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dw1 = 1 << CMD_HDR_VDTL_OFF;
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if (is_tmf) {
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dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
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dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
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} else {
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dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
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switch (scsi_cmnd->sc_data_direction) {
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case DMA_TO_DEVICE:
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has_data = 1;
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dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
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break;
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case DMA_FROM_DEVICE:
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has_data = 1;
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dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
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break;
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default:
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dw1 &= ~CMD_HDR_DIR_MSK;
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}
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}
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/* map itct entry */
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dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
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hdr->dw1 = cpu_to_le32(dw1);
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dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
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+ 3) / 4) << CMD_HDR_CFL_OFF) |
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((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
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(2 << CMD_HDR_SG_MOD_OFF);
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hdr->dw2 = cpu_to_le32(dw2);
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hdr->transfer_tags = cpu_to_le32(slot->idx);
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if (has_data) {
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rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
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slot->n_elem);
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if (rc)
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return rc;
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}
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hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
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hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
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hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
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buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
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memcpy(buf_cmd, ssp_task->LUN, 8);
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if (!is_tmf) {
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buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
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memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
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} else {
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buf_cmd[10] = tmf->tmf;
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switch (tmf->tmf) {
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case TMF_ABORT_TASK:
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case TMF_QUERY_TASK:
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buf_cmd[12] =
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(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
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buf_cmd[13] =
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tmf->tag_of_task_to_be_managed & 0xff;
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break;
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default:
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break;
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}
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}
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return 0;
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}
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static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
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{
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int i, res = 0;
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@ -1020,6 +1224,10 @@ static const struct hisi_sas_hw hisi_sas_v3_hw = {
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.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
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.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
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.sl_notify = sl_notify_v3_hw,
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.prep_ssp = prep_ssp_v3_hw,
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.get_free_slot = get_free_slot_v3_hw,
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.start_delivery = start_delivery_v3_hw,
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.slot_complete = slot_complete_v3_hw,
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.phys_init = phys_init_v3_hw,
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};
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