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ARM: dts: DRA7: Add PCIe related clock nodes

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This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
J Keerthy 2013-07-23 12:05:40 +05:30 committed by Mike Turquette
parent c3be7acdeb
commit a0289f9174
1 changed files with 25 additions and 0 deletions
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25
arch/arm/boot/dts/dra7xx-clocks.dtsi
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@ -1165,6 +1165,31 @@
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <9>;
};
optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";