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sh: SH-DMAC compile fixes
This patch does the following: - remove the make_ipr_irq stuff from dma-sh.c and replace it with a simple channel<->irq mapping table. - add DMTEx_IRQ constants for sh4 cpus - fix sh7751 DMAE irq number The SH7780 uses the same IRQs for DMA as other SH4 types, so I put the constants on top of the dma.h file. Other CPU types need to #define their own DMTEx_IRQ contants in their appropriate header. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -19,34 +19,26 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include "dma-sh.h"
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#include "dma-sh.h"
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static int dmte_irq_map[] = {
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DMTE0_IRQ,
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#ifdef CONFIG_CPU_SH4
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DMTE1_IRQ,
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static struct ipr_data dmae_ipr_map[] = {
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DMTE2_IRQ,
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{ DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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DMTE3_IRQ,
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};
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#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7760) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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DMTE4_IRQ,
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DMTE5_IRQ,
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DMTE6_IRQ,
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DMTE7_IRQ,
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#endif
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#endif
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static struct ipr_data dmte_ipr_map[] = {
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/*
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* Normally we could just do DMTE0_IRQ + chan outright, though in the
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* case of the 7751R, the DMTE IRQs for channels > 4 start right above
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* the SCIF
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*/
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{ DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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};
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};
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static inline unsigned int get_dmte_irq(unsigned int chan)
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static inline unsigned int get_dmte_irq(unsigned int chan)
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{
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{
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unsigned int irq = 0;
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unsigned int irq = 0;
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if (chan < ARRAY_SIZE(dmte_ipr_map))
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if (chan < ARRAY_SIZE(dmte_irq_map))
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irq = dmte_ipr_map[chan].irq;
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irq = dmte_irq_map[chan];
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return irq;
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return irq;
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}
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}
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@ -103,7 +95,7 @@ static void sh_dmac_free_dma(struct dma_channel *chan)
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free_irq(get_dmte_irq(chan->chan), chan);
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free_irq(get_dmte_irq(chan->chan), chan);
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}
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}
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static void
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static int
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sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
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sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
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{
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{
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if (!chcr)
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if (!chcr)
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@ -119,6 +111,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
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ctrl_outl(chcr, CHCR[chan->chan]);
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ctrl_outl(chcr, CHCR[chan->chan]);
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chan->flags |= DMA_CONFIGURED;
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chan->flags |= DMA_CONFIGURED;
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return 0;
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}
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}
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static void sh_dmac_enable_dma(struct dma_channel *chan)
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static void sh_dmac_enable_dma(struct dma_channel *chan)
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@ -262,17 +255,11 @@ static int __init sh_dmac_init(void)
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int i;
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int i;
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#ifdef CONFIG_CPU_SH4
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#ifdef CONFIG_CPU_SH4
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make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
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i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
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i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
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if (unlikely(i < 0))
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if (unlikely(i < 0))
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return i;
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return i;
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#endif
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#endif
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i = info->nr_channels;
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if (i > ARRAY_SIZE(dmte_ipr_map))
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i = ARRAY_SIZE(dmte_ipr_map);
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make_ipr_irq(dmte_ipr_map, i);
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/*
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/*
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* Initialize DMAOR, and clean up any error flags that may have
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* Initialize DMAOR, and clean up any error flags that may have
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* been set.
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* been set.
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@ -101,7 +101,7 @@ static struct ipr_data sh7750_ipr_map[] = {
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 28, 2, 8, 7 }, /* DMAC DMAE */
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{ 38, 2, 8, 7 }, /* DMAC DMAE */
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};
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};
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static struct ipr_data sh7751_ipr_map[] = {
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static struct ipr_data sh7751_ipr_map[] = {
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@ -3,6 +3,17 @@
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#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
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#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
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/* SH7751/7760/7780 DMA IRQ sources */
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#define DMTE0_IRQ 34
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#define DMTE1_IRQ 35
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#define DMTE2_IRQ 36
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#define DMTE3_IRQ 37
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#define DMTE4_IRQ 44
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#define DMTE5_IRQ 45
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#define DMTE6_IRQ 46
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#define DMTE7_IRQ 47
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#define DMAE_IRQ 38
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#ifdef CONFIG_CPU_SH4A
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#ifdef CONFIG_CPU_SH4A
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#define SH_DMAC_BASE 0xfc808020
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#define SH_DMAC_BASE 0xfc808020
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