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drm/radeon: minor sid.h cleanup
Consolidate the non-register defines. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -30,6 +30,24 @@
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#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
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#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
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#define SI_MAX_SH_GPRS 256
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#define SI_MAX_TEMP_GPRS 16
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#define SI_MAX_SH_THREADS 256
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#define SI_MAX_SH_STACK_ENTRIES 4096
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#define SI_MAX_FRC_EOV_CNT 16384
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#define SI_MAX_BACKENDS 8
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#define SI_MAX_BACKENDS_MASK 0xFF
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#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
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#define SI_MAX_SIMDS 12
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#define SI_MAX_SIMDS_MASK 0x0FFF
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#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
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#define SI_MAX_PIPES 8
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#define SI_MAX_PIPES_MASK 0xFF
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#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
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#define SI_MAX_LDS_NUM 0xFFFF
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#define SI_MAX_TCC 16
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#define SI_MAX_TCC_MASK 0xFFFF
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/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
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#define SMC_CG_IND_START 0xc0030000
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@ -73,24 +91,6 @@
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#define CTF_TEMP_MASK 0x0003fe00
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#define CTF_TEMP_SHIFT 9
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#define SI_MAX_SH_GPRS 256
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#define SI_MAX_TEMP_GPRS 16
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#define SI_MAX_SH_THREADS 256
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#define SI_MAX_SH_STACK_ENTRIES 4096
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#define SI_MAX_FRC_EOV_CNT 16384
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#define SI_MAX_BACKENDS 8
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#define SI_MAX_BACKENDS_MASK 0xFF
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#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
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#define SI_MAX_SIMDS 12
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#define SI_MAX_SIMDS_MASK 0x0FFF
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#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
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#define SI_MAX_PIPES 8
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#define SI_MAX_PIPES_MASK 0xFF
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#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
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#define SI_MAX_LDS_NUM 0xFFFF
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#define SI_MAX_TCC 16
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#define SI_MAX_TCC_MASK 0xFFFF
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#define VGA_HDP_CONTROL 0x328
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#define VGA_MEMORY_DISABLE (1 << 4)
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