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MIPS: Netlogic: Add support for USB on XLP2xx
Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5744/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam
Ralf Baechle
parent
e5be1fd007
commit
9eac3591e7
@ -72,6 +72,12 @@
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#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
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#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
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/* XLP2xx has an updated USB block */
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#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
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#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
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#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
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#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
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#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
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#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
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@ -148,6 +154,7 @@
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#define PCI_DEVICE_ID_NLM_NOR 0x1015
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#define PCI_DEVICE_ID_NLM_NAND 0x1016
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#define PCI_DEVICE_ID_NLM_MMC 0x1018
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#define PCI_DEVICE_ID_NLM_XHCI 0x101d
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#ifndef __ASSEMBLY__
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@ -41,12 +41,17 @@
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#define PIC_PCIE_LINK_1_IRQ 20
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#define PIC_PCIE_LINK_2_IRQ 21
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#define PIC_PCIE_LINK_3_IRQ 22
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#define PIC_EHCI_0_IRQ 23
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#define PIC_EHCI_1_IRQ 24
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#define PIC_OHCI_0_IRQ 25
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#define PIC_OHCI_1_IRQ 26
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#define PIC_OHCI_2_IRQ 27
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#define PIC_OHCI_3_IRQ 28
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#define PIC_2XX_XHCI_0_IRQ 23
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#define PIC_2XX_XHCI_1_IRQ 24
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#define PIC_2XX_XHCI_2_IRQ 25
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#define PIC_MMC_IRQ 29
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#define PIC_I2C_0_IRQ 30
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#define PIC_I2C_1_IRQ 31
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@ -1,3 +1,4 @@
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obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
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obj-$(CONFIG_SMP) += wakeup.o
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obj-$(CONFIG_USB) += usb-init.o
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obj-$(CONFIG_USB) += usb-init-xlp2.o
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@ -65,6 +65,7 @@ int nlm_irq_to_irt(int irq)
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uint64_t pcibase;
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int devoff, irt;
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devoff = 0;
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switch (irq) {
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case PIC_UART_0_IRQ:
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devoff = XLP_IO_UART0_OFFSET(0);
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@ -72,24 +73,6 @@ int nlm_irq_to_irt(int irq)
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case PIC_UART_1_IRQ:
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devoff = XLP_IO_UART1_OFFSET(0);
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break;
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case PIC_EHCI_0_IRQ:
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devoff = XLP_IO_USB_EHCI0_OFFSET(0);
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break;
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case PIC_EHCI_1_IRQ:
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devoff = XLP_IO_USB_EHCI1_OFFSET(0);
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break;
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case PIC_OHCI_0_IRQ:
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devoff = XLP_IO_USB_OHCI0_OFFSET(0);
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break;
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case PIC_OHCI_1_IRQ:
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devoff = XLP_IO_USB_OHCI1_OFFSET(0);
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break;
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case PIC_OHCI_2_IRQ:
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devoff = XLP_IO_USB_OHCI2_OFFSET(0);
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break;
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case PIC_OHCI_3_IRQ:
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devoff = XLP_IO_USB_OHCI3_OFFSET(0);
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break;
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case PIC_MMC_IRQ:
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devoff = XLP_IO_SD_OFFSET(0);
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break;
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@ -103,8 +86,41 @@ int nlm_irq_to_irt(int irq)
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devoff = XLP_IO_I2C0_OFFSET(0);
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break;
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default:
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devoff = 0;
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break;
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if (cpu_is_xlpii()) {
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switch (irq) {
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/* XLP2XX has three XHCI USB controller */
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case PIC_2XX_XHCI_0_IRQ:
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devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
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break;
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case PIC_2XX_XHCI_1_IRQ:
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devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
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break;
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case PIC_2XX_XHCI_2_IRQ:
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devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
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break;
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}
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} else {
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switch (irq) {
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case PIC_EHCI_0_IRQ:
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devoff = XLP_IO_USB_EHCI0_OFFSET(0);
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break;
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case PIC_EHCI_1_IRQ:
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devoff = XLP_IO_USB_EHCI1_OFFSET(0);
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break;
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case PIC_OHCI_0_IRQ:
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devoff = XLP_IO_USB_OHCI0_OFFSET(0);
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break;
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case PIC_OHCI_1_IRQ:
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devoff = XLP_IO_USB_OHCI1_OFFSET(0);
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break;
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case PIC_OHCI_2_IRQ:
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devoff = XLP_IO_USB_OHCI2_OFFSET(0);
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break;
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case PIC_OHCI_3_IRQ:
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devoff = XLP_IO_USB_OHCI3_OFFSET(0);
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break;
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}
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}
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}
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if (devoff != 0) {
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218
arch/mips/netlogic/xlp/usb-init-xlp2.c
Normal file
218
arch/mips/netlogic/xlp/usb-init-xlp2.c
Normal file
@ -0,0 +1,218 @@
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/*
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* Copyright (c) 2003-2013 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#define XLPII_USB3_CTL_0 0xc0
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#define XLPII_VAUXRST BIT(0)
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#define XLPII_VCCRST BIT(1)
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#define XLPII_NUM2PORT 9
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#define XLPII_NUM3PORT 13
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#define XLPII_RTUNEREQ BIT(20)
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#define XLPII_MS_CSYSREQ BIT(21)
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#define XLPII_XS_CSYSREQ BIT(22)
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#define XLPII_RETENABLEN BIT(23)
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#define XLPII_TX2RX BIT(24)
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#define XLPII_XHCIREV BIT(25)
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#define XLPII_ECCDIS BIT(26)
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#define XLPII_USB3_INT_REG 0xc2
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#define XLPII_USB3_INT_MASK 0xc3
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#define XLPII_USB_PHY_TEST 0xc6
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#define XLPII_PRESET BIT(0)
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#define XLPII_ATERESET BIT(1)
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#define XLPII_LOOPEN BIT(2)
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#define XLPII_TESTPDHSP BIT(3)
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#define XLPII_TESTPDSSP BIT(4)
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#define XLPII_TESTBURNIN BIT(5)
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#define XLPII_USB_PHY_LOS_LV 0xc9
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#define XLPII_LOSLEV 0
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#define XLPII_LOSBIAS 5
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#define XLPII_SQRXTX 8
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#define XLPII_TXBOOST 11
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#define XLPII_RSLKSEL 16
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#define XLPII_FSEL 20
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#define XLPII_USB_RFCLK_REG 0xcc
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#define XLPII_VVLD 30
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#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_xlpii_get_usb_pcibase(node, inst) \
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nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst))
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#define nlm_xlpii_get_usb_regbase(node, inst) \
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(nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
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static void xlpii_usb_ack(struct irq_data *data)
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{
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u64 port_addr;
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switch (data->irq) {
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case PIC_2XX_XHCI_0_IRQ:
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port_addr = nlm_xlpii_get_usb_regbase(0, 1);
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break;
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case PIC_2XX_XHCI_1_IRQ:
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port_addr = nlm_xlpii_get_usb_regbase(0, 2);
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break;
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case PIC_2XX_XHCI_2_IRQ:
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port_addr = nlm_xlpii_get_usb_regbase(0, 3);
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break;
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default:
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pr_err("No matching USB irq!\n");
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return;
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}
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nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
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}
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static void nlm_xlpii_usb_hw_reset(int node, int port)
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{
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u64 port_addr, xhci_base, pci_base;
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void __iomem *corebase;
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u32 val;
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port_addr = nlm_xlpii_get_usb_regbase(node, port);
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/* Set frequency */
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val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV);
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val &= ~(0x3f << XLPII_FSEL);
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val |= (0x27 << XLPII_FSEL);
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nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val);
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val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG);
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val |= (1 << XLPII_VVLD);
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nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val);
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/* PHY reset */
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val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST);
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val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP
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| XLPII_TESTPDSSP | XLPII_TESTBURNIN);
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nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val);
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/* Setup control register */
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val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT)
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| (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ
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| XLPII_RETENABLEN | XLPII_XHCIREV;
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nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val);
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/* Enable interrupts */
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nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001);
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/* Clear all interrupts */
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nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
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udelay(2000);
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/* XHCI configuration at PCI mem */
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pci_base = nlm_xlpii_get_usb_pcibase(node, port);
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xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf;
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corebase = ioremap(xhci_base, 0x10000);
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if (!corebase)
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return;
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writel(0x240002, corebase + 0xc2c0);
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/* GCTL 0xc110 */
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val = readl(corebase + 0xc110);
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val &= ~(0x3 << 12);
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val |= (1 << 12);
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writel(val, corebase + 0xc110);
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udelay(100);
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/* PHYCFG 0xc200 */
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val = readl(corebase + 0xc200);
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val &= ~(1 << 6);
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writel(val, corebase + 0xc200);
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udelay(100);
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/* PIPECTL 0xc2c0 */
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val = readl(corebase + 0xc2c0);
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val &= ~(1 << 17);
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writel(val, corebase + 0xc2c0);
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iounmap(corebase);
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}
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static int __init nlm_platform_xlpii_usb_init(void)
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{
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if (!cpu_is_xlpii())
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return 0;
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pr_info("Initializing 2XX USB Interface\n");
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nlm_xlpii_usb_hw_reset(0, 1);
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nlm_xlpii_usb_hw_reset(0, 2);
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nlm_xlpii_usb_hw_reset(0, 3);
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nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack);
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nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack);
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nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack);
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return 0;
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}
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arch_initcall(nlm_platform_xlpii_usb_init);
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static u64 xlp_usb_dmamask = ~(u32)0;
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/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */
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static void nlm_usb_fixup_final(struct pci_dev *dev)
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{
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dev->dev.dma_mask = &xlp_usb_dmamask;
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dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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switch (dev->devfn) {
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case 0x21:
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dev->irq = PIC_2XX_XHCI_0_IRQ;
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break;
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case 0x22:
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dev->irq = PIC_2XX_XHCI_1_IRQ;
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break;
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case 0x23:
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dev->irq = PIC_2XX_XHCI_2_IRQ;
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break;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
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nlm_usb_fixup_final);
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@ -99,6 +99,9 @@ static void nlm_usb_hw_reset(int node, int port)
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static int __init nlm_platform_usb_init(void)
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{
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if (cpu_is_xlpii())
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return 0;
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pr_info("Initializing USB Interface\n");
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nlm_usb_hw_reset(0, 0);
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nlm_usb_hw_reset(0, 3);
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