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Raw NAND controller driver change:
* Qcom: Update code word value for raw reads (QPIC v2+) -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmFpVGEACgkQJWrqGEe9 VoR5IggAj5dtbvVx89icuQp1yfBebZJXQGVvd06E1Btk36nic538SHnEkc3heiUZ ySxBiN8mKI/0wgOK3PBxRoSU9XNAl32W4AmG2nQzhfgL1AL0bCKlaOVuf305ts58 SGECfEawVNbMZKH/WFwsHQBMH+d+B8oMiWgK7h694OCWQxnQSTBYKCGEB9Dzqjjd 8l0oQBTgPGOFrb3p0P+GRFbSFy+wLPIQpU9hm1HoXQxZk7K6fSkPqjTYP8FUI8Nc bAaQTM7Y2rA2GyandlhUnEkQICu1P1MEVxh9viNYyPKb9Lu85F7mpDa8kCPxq3LS 67X9gJO+PIzvW0wy6zsSWTWC8giaGg== =gtld -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-5.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd fix from Miquel Raynal: "Raw NAND controller driver fix: - Qcom: Update code word value for raw reads (QPIC v2+)" * tag 'mtd/fixes-for-5.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: rawnand: qcom: Update code word value for raw read
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commit
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@ -1676,13 +1676,17 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int data_size1, data_size2, oob_size1, oob_size2;
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int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
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int raw_cw = cw;
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nand_read_page_op(chip, page, 0, NULL, 0);
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host->use_ecc = false;
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if (nandc->props->qpic_v2)
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raw_cw = ecc->steps - 1;
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clear_bam_transaction(nandc);
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set_address(host, host->cw_size * cw, page);
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update_rw_regs(host, 1, true, cw);
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update_rw_regs(host, 1, true, raw_cw);
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config_nand_page_read(chip);
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data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
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@ -1711,7 +1715,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
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nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
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}
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config_nand_cw_read(chip, false, cw);
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config_nand_cw_read(chip, false, raw_cw);
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read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
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reg_off += data_size1;
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