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crypto: hisilicon - register zip engine to uacce
Register qm to uacce framework for user crypto driver Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Zhangfei Gao
Herbert Xu
parent
18bead70e9
commit
9e00df7156
@ -9,6 +9,9 @@
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#include <linux/log2.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/uacce.h>
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#include <linux/uaccess.h>
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#include <uapi/misc/uacce/hisi_qm.h>
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#include "qm.h"
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/* eq/aeq irq enable */
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@ -466,9 +469,14 @@ static void qm_cq_head_update(struct hisi_qp *qp)
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static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
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{
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struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
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if (qp->event_cb) {
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qp->event_cb(qp);
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return;
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}
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if (qp->req_cb) {
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struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
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while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
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dma_rmb();
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qp->req_cb(qp, qp->sqe + qm->sqe_size *
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@ -1273,7 +1281,7 @@ static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, int pasid)
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* @qp: The qp we want to start to run.
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* @arg: Accelerator specific argument.
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*
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* After this function, qp can receive request from user. Return qp_id if
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* After this function, qp can receive request from user. Return 0 if
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* successful, Return -EBUSY if failed.
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*/
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int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
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@ -1318,7 +1326,7 @@ int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
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dev_dbg(dev, "queue %d started\n", qp_id);
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return qp_id;
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return 0;
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}
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EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
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@ -1399,6 +1407,214 @@ static void hisi_qm_cache_wb(struct hisi_qm *qm)
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}
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}
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static void qm_qp_event_notifier(struct hisi_qp *qp)
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{
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wake_up_interruptible(&qp->uacce_q->wait);
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}
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static int hisi_qm_get_available_instances(struct uacce_device *uacce)
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{
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int i, ret;
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struct hisi_qm *qm = uacce->priv;
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read_lock(&qm->qps_lock);
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for (i = 0, ret = 0; i < qm->qp_num; i++)
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if (!qm->qp_array[i])
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ret++;
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read_unlock(&qm->qps_lock);
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return ret;
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}
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static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
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unsigned long arg,
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struct uacce_queue *q)
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{
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struct hisi_qm *qm = uacce->priv;
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struct hisi_qp *qp;
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u8 alg_type = 0;
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qp = hisi_qm_create_qp(qm, alg_type);
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if (IS_ERR(qp))
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return PTR_ERR(qp);
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q->priv = qp;
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q->uacce = uacce;
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qp->uacce_q = q;
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qp->event_cb = qm_qp_event_notifier;
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qp->pasid = arg;
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return 0;
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}
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static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
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{
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struct hisi_qp *qp = q->priv;
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hisi_qm_cache_wb(qp->qm);
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hisi_qm_release_qp(qp);
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}
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/* map sq/cq/doorbell to user space */
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static int hisi_qm_uacce_mmap(struct uacce_queue *q,
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struct vm_area_struct *vma,
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struct uacce_qfile_region *qfr)
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{
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struct hisi_qp *qp = q->priv;
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struct hisi_qm *qm = qp->qm;
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size_t sz = vma->vm_end - vma->vm_start;
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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unsigned long vm_pgoff;
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int ret;
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switch (qfr->type) {
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case UACCE_QFRT_MMIO:
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if (qm->ver == QM_HW_V2) {
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if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
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QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
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return -EINVAL;
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} else {
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if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
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return -EINVAL;
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}
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vma->vm_flags |= VM_IO;
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return remap_pfn_range(vma, vma->vm_start,
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qm->phys_base >> PAGE_SHIFT,
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sz, pgprot_noncached(vma->vm_page_prot));
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case UACCE_QFRT_DUS:
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if (sz != qp->qdma.size)
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return -EINVAL;
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/*
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* dma_mmap_coherent() requires vm_pgoff as 0
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* restore vm_pfoff to initial value for mmap()
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*/
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vm_pgoff = vma->vm_pgoff;
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vma->vm_pgoff = 0;
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ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
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qp->qdma.dma, sz);
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vma->vm_pgoff = vm_pgoff;
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return ret;
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default:
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return -EINVAL;
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}
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}
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static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
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{
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struct hisi_qp *qp = q->priv;
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return hisi_qm_start_qp(qp, qp->pasid);
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}
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static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
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{
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hisi_qm_stop_qp(q->priv);
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}
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static int qm_set_sqctype(struct uacce_queue *q, u16 type)
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{
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struct hisi_qm *qm = q->uacce->priv;
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struct hisi_qp *qp = q->priv;
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write_lock(&qm->qps_lock);
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qp->alg_type = type;
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write_unlock(&qm->qps_lock);
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return 0;
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}
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static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
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unsigned long arg)
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{
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struct hisi_qp *qp = q->priv;
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struct hisi_qp_ctx qp_ctx;
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if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
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if (copy_from_user(&qp_ctx, (void __user *)arg,
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sizeof(struct hisi_qp_ctx)))
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return -EFAULT;
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if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1)
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return -EINVAL;
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qm_set_sqctype(q, qp_ctx.qc_type);
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qp_ctx.id = qp->qp_id;
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if (copy_to_user((void __user *)arg, &qp_ctx,
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sizeof(struct hisi_qp_ctx)))
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return -EFAULT;
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static const struct uacce_ops uacce_qm_ops = {
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.get_available_instances = hisi_qm_get_available_instances,
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.get_queue = hisi_qm_uacce_get_queue,
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.put_queue = hisi_qm_uacce_put_queue,
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.start_queue = hisi_qm_uacce_start_queue,
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.stop_queue = hisi_qm_uacce_stop_queue,
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.mmap = hisi_qm_uacce_mmap,
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.ioctl = hisi_qm_uacce_ioctl,
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};
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static int qm_alloc_uacce(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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struct uacce_device *uacce;
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unsigned long mmio_page_nr;
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unsigned long dus_page_nr;
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struct uacce_interface interface = {
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.flags = UACCE_DEV_SVA,
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.ops = &uacce_qm_ops,
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};
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strncpy(interface.name, pdev->driver->name, sizeof(interface.name));
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uacce = uacce_alloc(&pdev->dev, &interface);
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if (IS_ERR(uacce))
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return PTR_ERR(uacce);
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if (uacce->flags & UACCE_DEV_SVA) {
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qm->use_sva = true;
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} else {
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/* only consider sva case */
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uacce_remove(uacce);
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qm->uacce = NULL;
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return -EINVAL;
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}
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uacce->is_vf = pdev->is_virtfn;
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uacce->priv = qm;
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uacce->algs = qm->algs;
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if (qm->ver == QM_HW_V1) {
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mmio_page_nr = QM_DOORBELL_PAGE_NR;
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uacce->api_ver = HISI_QM_API_VER_BASE;
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} else {
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mmio_page_nr = QM_DOORBELL_PAGE_NR +
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QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
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uacce->api_ver = HISI_QM_API_VER2_BASE;
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}
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dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
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sizeof(struct qm_cqe) * QM_Q_DEPTH) >> PAGE_SHIFT;
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uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
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uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
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qm->uacce = uacce;
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return 0;
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}
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/**
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* hisi_qm_get_free_qp_num() - Get free number of qp in qm.
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* @qm: The qm which want to get free qp.
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@ -1441,10 +1657,14 @@ int hisi_qm_init(struct hisi_qm *qm)
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return -EINVAL;
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}
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ret = qm_alloc_uacce(qm);
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if (ret < 0)
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dev_warn(&pdev->dev, "fail to alloc uacce (%d)\n", ret);
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ret = pci_enable_device_mem(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to enable device mem!\n");
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return ret;
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goto err_remove_uacce;
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}
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ret = pci_request_mem_regions(pdev, qm->dev_name);
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@ -1453,8 +1673,9 @@ int hisi_qm_init(struct hisi_qm *qm)
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goto err_disable_pcidev;
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}
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qm->io_base = ioremap(pci_resource_start(pdev, PCI_BAR_2),
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pci_resource_len(qm->pdev, PCI_BAR_2));
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qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
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qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
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qm->io_base = ioremap(qm->phys_base, qm->phys_size);
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if (!qm->io_base) {
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ret = -EIO;
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goto err_release_mem_regions;
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@ -1497,6 +1718,9 @@ err_release_mem_regions:
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pci_release_mem_regions(pdev);
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err_disable_pcidev:
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pci_disable_device(pdev);
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err_remove_uacce:
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uacce_remove(qm->uacce);
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qm->uacce = NULL;
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return ret;
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}
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@ -1513,6 +1737,9 @@ void hisi_qm_uninit(struct hisi_qm *qm)
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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uacce_remove(qm->uacce);
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qm->uacce = NULL;
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if (qm->use_dma_api && qm->qdma.va) {
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hisi_qm_cache_wb(qm);
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dma_free_coherent(dev, qm->qdma.size,
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@ -77,6 +77,9 @@
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#define HISI_ACC_SGL_SGE_NR_MAX 255
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/* page number for queue file region */
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#define QM_DOORBELL_PAGE_NR 1
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enum qp_state {
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QP_STOP,
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};
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@ -180,7 +183,12 @@ struct hisi_qm {
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u32 error_mask;
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u32 msi_mask;
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const char *algs;
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bool use_dma_api;
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bool use_sva;
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resource_size_t phys_base;
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resource_size_t phys_size;
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struct uacce_device *uacce;
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};
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struct hisi_qp_status {
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@ -210,10 +218,13 @@ struct hisi_qp {
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struct hisi_qp_ops *hw_ops;
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void *qp_ctx;
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void (*req_cb)(struct hisi_qp *qp, void *data);
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void (*event_cb)(struct hisi_qp *qp);
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struct work_struct work;
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struct workqueue_struct *wq;
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struct hisi_qm *qm;
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u16 pasid;
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struct uacce_queue *uacce_q;
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};
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int hisi_qm_init(struct hisi_qm *qm);
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@ -11,6 +11,7 @@
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#include <linux/pci.h>
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#include <linux/seq_file.h>
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#include <linux/topology.h>
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#include <linux/uacce.h>
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#include "zip.h"
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#define PCI_DEVICE_ID_ZIP_PF 0xa250
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@ -354,8 +355,14 @@ static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
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writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
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if (hisi_zip->qm.use_sva) {
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writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
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writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
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} else {
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writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
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writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
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}
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/* let's open all compression/decompression cores */
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writel(DECOMP_CHECK_ENABLE | ALL_COMP_DECOMP_EN,
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@ -842,6 +849,7 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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qm->pdev = pdev;
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qm->ver = rev_id;
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qm->algs = "zlib\ngzip";
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qm->sqe_size = HZIP_SQE_SIZE;
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qm->dev_name = hisi_zip_name;
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qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? QM_HW_PF :
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@ -885,6 +893,12 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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hisi_zip_add_to_list(hisi_zip);
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if (qm->uacce) {
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ret = uacce_register(qm->uacce);
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if (ret)
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goto err_qm_uninit;
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}
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if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
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ret = hisi_zip_sriov_enable(pdev, vfs_num);
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if (ret < 0)
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23
include/uapi/misc/uacce/hisi_qm.h
Normal file
23
include/uapi/misc/uacce/hisi_qm.h
Normal file
@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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#ifndef _UAPI_HISI_QM_H
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#define _UAPI_HISI_QM_H
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#include <linux/types.h>
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/**
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* struct hisi_qp_ctx - User data for hisi qp.
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* @id: qp_index return to user space
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* @qc_type: Accelerator algorithm type
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*/
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struct hisi_qp_ctx {
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__u16 id;
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__u16 qc_type;
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};
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#define HISI_QM_API_VER_BASE "hisi_qm_v1"
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#define HISI_QM_API_VER2_BASE "hisi_qm_v2"
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/* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */
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#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
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#endif
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