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interconnect changes for 6.12

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This pull request contains the interconnect changes for the 6.12-rc1 merge
 window. It contains new drivers and fixes with the following highlights:
 
 Driver changes:
 - New driver for MSM8976 platforms
 - New driver for MSM8937 platforms
 - Enable sync_state for SM8250 platforms
 - Enable QoS support for QCS404
 - Add ab_coeff bandwidth adjustments for MSM8953
 - Drop the unsupported yet DISP nodes on SM8350 platforms
 - Fix missed num_nodes initialization in icc-clk driver
 - Misc DT and documentation fixes
 
 Signed-off-by: Georgi Djakov <djakov@kernel.org>
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJm2yFVAAoJEIDQzArG2BZjftcP/iGk0eWtU4Y6NA539spBssDL
 9WLFT2vj7KM9t+Ox+k+b/Gqzrhcg6R/8GvEDuf/BmkueqjO8XMIBY31NefDnAbzk
 /oWZF5hS1MEHo1ok1+FsjZ6HUmNfNiVBXy/2d59BegWlNex8VQKqpt/cx2ZIZuoi
 F6XoBNzLROwCpLKVPAizGa04cfvrqynkIUYFl9Tho44yjsyFRJxjLlvmcCvh56TH
 svbaD7QHjHcA/18QhFRG5yA4+4MZorXy754GGTvV0QExm8Mc2Pn5IbhAARGFC1Ir
 N4FzXkc1pfsmfMAkDhpBZtbtarGJHt74MStlLXyPkiLVZOxc4M4oQWSP3CxS01zn
 5/pYenOBoO/YNClCM2PEK08PNNvoQxtebQJ36VJyh6HugHYKu2qqSHVtHm/cOY5l
 cAPfJNrsFPqI4zjrdAgt63AhM+80+u0Z2YN5Oy8e1+gBvzrSf/pIqB+bdPgbs2CI
 JxYc2LBJ2+9bS718TcjiiacHdpQCo1JV5mt1fwvupRG4yuOM1O5Y/xbDowQIAb7q
 +NEwu9KxI2uVvscmv7WfHS5ZlTTec3/ri2OFf7CmY4pYNnTuzoT9C4I1kMtD4BCT
 jcgCZXFeB+thkQ29pDtexeRxGdIYLa34T+BzfZQ+ipchqHGXVdne5QuSkH0syV/r
 7wtCXwWzLXf1uPFCrFZy
 =ckcc
 -----END PGP SIGNATURE-----

Merge tag 'icc-6.12-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Georgi writes:

interconnect changes for 6.12

This pull request contains the interconnect changes for the 6.12-rc1 merge
window. It contains new drivers and fixes with the following highlights:

Driver changes:
- New driver for MSM8976 platforms
- New driver for MSM8937 platforms
- Enable sync_state for SM8250 platforms
- Enable QoS support for QCS404
- Add ab_coeff bandwidth adjustments for MSM8953
- Drop the unsupported yet DISP nodes on SM8350 platforms
- Fix missed num_nodes initialization in icc-clk driver
- Misc DT and documentation fixes

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-6.12-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  dt-bindings: interconnect: qcom: Do not require reg for sc8180x virt NoCs
  dt-bindings: interconnect: qcom-bwmon: Document SA8775p bwmon compatibles
  dt-bindings: interconnect: qcom: msm8953: Fix 'See also' in description
  interconnect: qcom: msm8953: Add ab_coeff
  dt-bindings: interconnect: qcom: msm8939: Fix example
  interconnect: qcom: qcs404: Add regmaps and more bus descriptions
  interconnect: qcom: qcs404: Mark AP-owned nodes as such
  interconnect: qcom: Add MSM8937 interconnect provider driver
  interconnect: qcom: sm8250: Enable sync_state
  dt-bindings: interconnect: qcom,sm8350: drop DISP nodes
  interconnect: qcom: sm8350: drop DISP nodes
  dt-bindings: interconnect: qcom: Add Qualcomm MSM8937 NoC
  interconnect: qcom: Add MSM8976 interconnect provider driver
  dt-bindings: interconnect: qcom: Add Qualcomm MSM8976 NoC
  interconnect: icc-clk: Add missed num_nodes initialization
  dt-bindings: interconnect: qcom,rpmh: correct sm8150 camnoc
This commit is contained in:
Greg Kroah-Hartman 2024-09-06 19:17:16 +02:00
commit 9d06852b24
16 changed files with 3151 additions and 193 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml
View File

@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8939 Network-On-Chip interconnect
title: Qualcomm MSM8937/MSM8939/MSM8976 Network-On-Chip interconnect
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description: |
The Qualcomm MSM8939 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
description:
The Qualcomm MSM8937/MSM8939/MSM8976 interconnect providers support
adjusting the bandwidth requirements between the various NoC fabrics.
allOf:
- $ref: qcom,rpm-common.yaml#
@ -19,9 +19,15 @@ allOf:
properties:
compatible:
enum:
- qcom,msm8937-bimc
- qcom,msm8937-pcnoc
- qcom,msm8937-snoc
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8976-bimc
- qcom,msm8976-pcnoc
- qcom,msm8976-snoc
reg:
maxItems: 1
@ -39,7 +45,10 @@ patternProperties:
properties:
compatible:
const: qcom,msm8939-snoc-mm
enum:
- qcom,msm8937-snoc-mm
- qcom,msm8939-snoc-mm
- qcom,msm8976-snoc-mm
required:
- compatible
@ -60,12 +69,6 @@ examples:
compatible = "qcom,msm8939-snoc";
reg = <0x00580000 0x14000>;
#interconnect-cells = <1>;
};
bimc: interconnect@400000 {
compatible = "qcom,msm8939-bimc";
reg = <0x00400000 0x62000>;
#interconnect-cells = <1>;
snoc_mm: interconnect-snoc {
compatible = "qcom,msm8939-snoc-mm";

3
Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml
View File

@ -13,8 +13,7 @@ description: |
The Qualcomm MSM8953 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
See also:
- dt-bindings/interconnect/qcom,msm8953.h
See also: include/dt-bindings/interconnect/qcom,msm8953.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@ -26,6 +26,7 @@ properties:
- items:
- enum:
- qcom,qcm2290-cpu-bwmon
- qcom,sa8775p-cpu-bwmon
- qcom,sc7180-cpu-bwmon
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
@ -39,6 +40,7 @@ properties:
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
- qcom,sa8775p-llcc-bwmon
- qcom,sc7180-llcc-bwmon
- qcom,sc8280xp-llcc-bwmon
- qcom,sm6350-cpu-bwmon

5
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View File

@ -71,7 +71,7 @@ properties:
- qcom,sdx65-system-noc
- qcom,sm8150-aggre1-noc
- qcom,sm8150-aggre2-noc
- qcom,sm8150-camnoc-noc
- qcom,sm8150-camnoc-virt
- qcom,sm8150-compute-noc
- qcom,sm8150-config-noc
- qcom,sm8150-dc-noc
@ -113,6 +113,9 @@ allOf:
properties:
compatible:
enum:
- qcom,sc8180x-camnoc-virt
- qcom,sc8180x-mc-virt
- qcom,sc8180x-qup-virt
- qcom,sdx65-mc-virt
- qcom,sm8250-qup-virt
then:

3
drivers/interconnect/icc-clk.c
View File

@ -87,6 +87,7 @@ struct icc_provider *icc_clk_register(struct device *dev,
onecell = devm_kzalloc(dev, struct_size(onecell, nodes, 2 * num_clocks), GFP_KERNEL);
if (!onecell)
return ERR_PTR(-ENOMEM);
onecell->num_nodes = 2 * num_clocks;
qp = devm_kzalloc(dev, struct_size(qp, clocks, num_clocks), GFP_KERNEL);
if (!qp)
@ -133,8 +134,6 @@ struct icc_provider *icc_clk_register(struct device *dev,
onecell->nodes[j++] = node;
}
onecell->num_nodes = j;
ret = icc_provider_register(provider);
if (ret)
goto err;

18
drivers/interconnect/qcom/Kconfig
View File

@ -26,6 +26,15 @@ config INTERCONNECT_QCOM_MSM8916
This is a driver for the Qualcomm Network-on-Chip on msm8916-based
platforms.
config INTERCONNECT_QCOM_MSM8937
tristate "Qualcomm MSM8937 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on msm8937-based
platforms.
config INTERCONNECT_QCOM_MSM8939
tristate "Qualcomm MSM8939 interconnect driver"
depends on INTERCONNECT_QCOM
@ -53,6 +62,15 @@ config INTERCONNECT_QCOM_MSM8974
This is a driver for the Qualcomm Network-on-Chip on msm8974-based
platforms.
config INTERCONNECT_QCOM_MSM8976
tristate "Qualcomm MSM8976 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on msm8976-based
platforms.
config INTERCONNECT_QCOM_MSM8996
tristate "Qualcomm MSM8996 interconnect driver"
depends on INTERCONNECT_QCOM

4
drivers/interconnect/qcom/Makefile
View File

@ -6,9 +6,11 @@ interconnect_qcom-y := icc-common.o
icc-bcm-voter-objs := bcm-voter.o
qnoc-msm8909-objs := msm8909.o
qnoc-msm8916-objs := msm8916.o
qnoc-msm8937-objs := msm8937.o
qnoc-msm8939-objs := msm8939.o
qnoc-msm8953-objs := msm8953.o
qnoc-msm8974-objs := msm8974.o
qnoc-msm8976-objs := msm8976.o
qnoc-msm8996-objs := msm8996.o
icc-osm-l3-objs := osm-l3.o
qnoc-qcm2290-objs := qcm2290.o
@ -41,9 +43,11 @@ icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) += qnoc-msm8937.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) += qnoc-msm8953.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) += qnoc-msm8976.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o

1350
drivers/interconnect/qcom/msm8937.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/interconnect/qcom/msm8953.c
View File

@ -1169,6 +1169,7 @@ static const struct qcom_icc_desc msm8953_bimc = {
.nodes = msm8953_bimc_nodes,
.num_nodes = ARRAY_SIZE(msm8953_bimc_nodes),
.qos_offset = 0x8000,
.ab_coeff = 153,
.regmap_cfg = &msm8953_bimc_regmap_config
};
@ -1295,6 +1296,7 @@ static const struct qcom_icc_desc msm8953_snoc_mm = {
.nodes = msm8953_snoc_mm_nodes,
.num_nodes = ARRAY_SIZE(msm8953_snoc_mm_nodes),
.qos_offset = 0x7000,
.ab_coeff = 153,
.regmap_cfg = &msm8953_snoc_regmap_config,
};

1440
drivers/interconnect/qcom/msm8976.c Normal file
View File

File diff suppressed because it is too large Load Diff

127
drivers/interconnect/qcom/qcs404.c
View File

@ -10,6 +10,7 @@
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "icc-rpm.h"
@ -101,6 +102,11 @@ static struct qcom_icc_node mas_apps_proc = {
.buswidth = 8,
.mas_rpm_id = 0,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 0,
.qos.prio_level = 0,
.qos.qos_port = 0,
.num_links = ARRAY_SIZE(mas_apps_proc_links),
.links = mas_apps_proc_links,
};
@ -116,6 +122,11 @@ static struct qcom_icc_node mas_oxili = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 0,
.qos.prio_level = 0,
.qos.qos_port = 2,
.num_links = ARRAY_SIZE(mas_oxili_links),
.links = mas_oxili_links,
};
@ -131,6 +142,11 @@ static struct qcom_icc_node mas_mdp = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 0,
.qos.prio_level = 1,
.qos.qos_port = 4,
.num_links = ARRAY_SIZE(mas_mdp_links),
.links = mas_mdp_links,
};
@ -145,6 +161,10 @@ static struct qcom_icc_node mas_snoc_bimc_1 = {
.buswidth = 8,
.mas_rpm_id = 76,
.slv_rpm_id = -1,
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
.qos.areq_prio = 0,
.qos.prio_level = 0,
.qos.qos_port = 5,
.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
.links = mas_snoc_bimc_1_links,
};
@ -160,6 +180,11 @@ static struct qcom_icc_node mas_tcu_0 = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 0,
.qos.prio_level = 2,
.qos.qos_port = 6,
.num_links = ARRAY_SIZE(mas_tcu_0_links),
.links = mas_tcu_0_links,
};
@ -174,6 +199,8 @@ static struct qcom_icc_node mas_spdm = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
.num_links = ARRAY_SIZE(mas_spdm_links),
.links = mas_spdm_links,
};
@ -231,6 +258,11 @@ static struct qcom_icc_node mas_crypto = {
.buswidth = 8,
.mas_rpm_id = 23,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 0,
.num_links = ARRAY_SIZE(mas_crypto_links),
.links = mas_crypto_links,
};
@ -287,6 +319,11 @@ static struct qcom_icc_node mas_qpic = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 14,
.num_links = ARRAY_SIZE(mas_qpic_links),
.links = mas_qpic_links,
};
@ -301,6 +338,11 @@ static struct qcom_icc_node mas_qdss_bam = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 1,
.num_links = ARRAY_SIZE(mas_qdss_bam_links),
.links = mas_qdss_bam_links,
};
@ -348,6 +390,11 @@ static struct qcom_icc_node mas_qdss_etr = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 0,
.num_links = ARRAY_SIZE(mas_qdss_etr_links),
.links = mas_qdss_etr_links,
};
@ -363,6 +410,11 @@ static struct qcom_icc_node mas_emac = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 17,
.num_links = ARRAY_SIZE(mas_emac_links),
.links = mas_emac_links,
};
@ -378,6 +430,11 @@ static struct qcom_icc_node mas_pcie = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 8,
.num_links = ARRAY_SIZE(mas_pcie_links),
.links = mas_pcie_links,
};
@ -393,6 +450,11 @@ static struct qcom_icc_node mas_usb3 = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 1,
.qos.prio_level = 1,
.qos.qos_port = 16,
.num_links = ARRAY_SIZE(mas_usb3_links),
.links = mas_usb3_links,
};
@ -491,6 +553,8 @@ static struct qcom_icc_node pcnoc_s_2 = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
.num_links = ARRAY_SIZE(pcnoc_s_2_links),
.links = pcnoc_s_2_links,
};
@ -626,6 +690,8 @@ static struct qcom_icc_node qdss_int = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
.num_links = ARRAY_SIZE(qdss_int_links),
.links = qdss_int_links,
};
@ -704,6 +770,8 @@ static struct qcom_icc_node slv_spdm = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_pdm = {
@ -752,6 +820,8 @@ static struct qcom_icc_node slv_disp_ss_cfg = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_gpu_cfg = {
@ -760,6 +830,8 @@ static struct qcom_icc_node slv_gpu_cfg = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_blsp_1 = {
@ -784,6 +856,8 @@ static struct qcom_icc_node slv_pcie = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_ethernet = {
@ -792,6 +866,8 @@ static struct qcom_icc_node slv_ethernet = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_blsp_2 = {
@ -816,6 +892,8 @@ static struct qcom_icc_node slv_tcu = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_pmic_arb = {
@ -894,6 +972,8 @@ static struct qcom_icc_node slv_kpss_ahb = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_wcss = {
@ -954,6 +1034,8 @@ static struct qcom_icc_node slv_cats_0 = {
.buswidth = 16,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_cats_1 = {
@ -962,6 +1044,8 @@ static struct qcom_icc_node slv_cats_1 = {
.buswidth = 8,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node slv_lpass = {
@ -970,6 +1054,8 @@ static struct qcom_icc_node slv_lpass = {
.buswidth = 4,
.mas_rpm_id = -1,
.slv_rpm_id = -1,
.qos.ap_owned = true,
.qos.qos_mode = NOC_QOS_MODE_INVALID,
};
static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
@ -982,10 +1068,22 @@ static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
};
static const struct regmap_config qcs404_bimc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static const struct qcom_icc_desc qcs404_bimc = {
.bus_clk_desc = &bimc_clk,
.type = QCOM_ICC_BIMC,
.nodes = qcs404_bimc_nodes,
.num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
.bus_clk_desc = &bimc_clk,
.regmap_cfg = &qcs404_bimc_regmap_config,
.qos_offset = 0x8000,
.ab_coeff = 153,
};
static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
@ -1037,10 +1135,22 @@ static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
[SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
};
static const struct regmap_config qcs404_pcnoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x15080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs404_pcnoc = {
.bus_clk_desc = &bus_0_clk,
.type = QCOM_ICC_NOC,
.nodes = qcs404_pcnoc_nodes,
.num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
.bus_clk_desc = &bus_0_clk,
.qos_offset = 0x7000,
.keep_alive = true,
.regmap_cfg = &qcs404_pcnoc_regmap_config,
};
static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
@ -1066,10 +1176,21 @@ static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
[SLAVE_LPASS] = &slv_lpass,
};
static const struct regmap_config qcs404_snoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x23080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs404_snoc = {
.bus_clk_desc = &bus_1_clk,
.type = QCOM_ICC_NOC,
.nodes = qcs404_snoc_nodes,
.num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
.bus_clk_desc = &bus_1_clk,
.qos_offset = 0x11000,
.regmap_cfg = &qcs404_snoc_regmap_config,
};

155
drivers/interconnect/qcom/sm8350.c
View File

@ -628,60 +628,6 @@ static struct qcom_icc_node xm_gic = {
.links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
};
static struct qcom_icc_node qnm_mnoc_hf_disp = {
.name = "qnm_mnoc_hf_disp",
.id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_SLAVE_LLCC_DISP },
};
static struct qcom_icc_node qnm_mnoc_sf_disp = {
.name = "qnm_mnoc_sf_disp",
.id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_SLAVE_LLCC_DISP },
};
static struct qcom_icc_node llcc_mc_disp = {
.name = "llcc_mc_disp",
.id = SM8350_MASTER_LLCC_DISP,
.channels = 4,
.buswidth = 4,
.num_links = 1,
.links = { SM8350_SLAVE_EBI1_DISP },
};
static struct qcom_icc_node qxm_mdp0_disp = {
.name = "qxm_mdp0_disp",
.id = SM8350_MASTER_MDP0_DISP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
};
static struct qcom_icc_node qxm_mdp1_disp = {
.name = "qxm_mdp1_disp",
.id = SM8350_MASTER_MDP1_DISP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
};
static struct qcom_icc_node qxm_rot_disp = {
.name = "qxm_rot_disp",
.id = SM8350_MASTER_ROTATOR_DISP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
.id = SM8350_SLAVE_A1NOC_SNOC,
@ -1320,40 +1266,6 @@ static struct qcom_icc_node srvc_snoc = {
.buswidth = 4,
};
static struct qcom_icc_node qns_llcc_disp = {
.name = "qns_llcc_disp",
.id = SM8350_SLAVE_LLCC_DISP,
.channels = 4,
.buswidth = 16,
.num_links = 1,
.links = { SM8350_MASTER_LLCC_DISP },
};
static struct qcom_icc_node ebi_disp = {
.name = "ebi_disp",
.id = SM8350_SLAVE_EBI1_DISP,
.channels = 4,
.buswidth = 4,
};
static struct qcom_icc_node qns_mem_noc_hf_disp = {
.name = "qns_mem_noc_hf_disp",
.id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP },
};
static struct qcom_icc_node qns_mem_noc_sf_disp = {
.name = "qns_mem_noc_sf_disp",
.id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
@ -1583,55 +1495,6 @@ static struct qcom_icc_bcm bcm_sn14 = {
.nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
.keepalive = false,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
static struct qcom_icc_bcm bcm_mc0_disp = {
.name = "MC0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
static struct qcom_icc_bcm bcm_mm0_disp = {
.name = "MM0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_disp },
};
static struct qcom_icc_bcm bcm_mm1_disp = {
.name = "MM1",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
};
static struct qcom_icc_bcm bcm_mm4_disp = {
.name = "MM4",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_mem_noc_sf_disp },
};
static struct qcom_icc_bcm bcm_mm5_disp = {
.name = "MM5",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_rot_disp },
};
static struct qcom_icc_bcm bcm_sh0_disp = {
.name = "SH0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_llcc_disp },
};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
};
@ -1785,7 +1648,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = {
&bcm_sh2,
&bcm_sh3,
&bcm_sh4,
&bcm_sh0_disp,
};
static struct qcom_icc_node * const gem_noc_nodes[] = {
@ -1808,9 +1670,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
};
static const struct qcom_icc_desc sm8350_gem_noc = {
@ -1843,15 +1702,11 @@ static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
&bcm_acv_disp,
&bcm_mc0_disp,
};
static struct qcom_icc_node * const mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI1] = &ebi,
[MASTER_LLCC_DISP] = &llcc_mc_disp,
[SLAVE_EBI1_DISP] = &ebi_disp,
};
static const struct qcom_icc_desc sm8350_mc_virt = {
@ -1866,10 +1721,6 @@ static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
&bcm_mm1,
&bcm_mm4,
&bcm_mm5,
&bcm_mm0_disp,
&bcm_mm1_disp,
&bcm_mm4_disp,
&bcm_mm5_disp,
};
static struct qcom_icc_node * const mmss_noc_nodes[] = {
@ -1886,11 +1737,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
[MASTER_MDP0_DISP] = &qxm_mdp0_disp,
[MASTER_MDP1_DISP] = &qxm_mdp1_disp,
[MASTER_ROTATOR_DISP] = &qxm_rot_disp,
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
};
static const struct qcom_icc_desc sm8350_mmss_noc = {
@ -1965,6 +1811,7 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sm8350",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

10
drivers/interconnect/qcom/sm8350.h
View File

@ -154,15 +154,5 @@
#define SM8350_SLAVE_PCIE_1 143
#define SM8350_SLAVE_QDSS_STM 144
#define SM8350_SLAVE_TCU 145
#define SM8350_MASTER_LLCC_DISP 146
#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147
#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148
#define SM8350_MASTER_MDP0_DISP 149
#define SM8350_MASTER_MDP1_DISP 150
#define SM8350_MASTER_ROTATOR_DISP 151
#define SM8350_SLAVE_EBI1_DISP 152
#define SM8350_SLAVE_LLCC_DISP 153
#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154
#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155
#endif

93
include/dt-bindings/interconnect/qcom,msm8937.h Normal file
View File

@ -0,0 +1,93 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Qualcomm MSM8937 interconnect IDs
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H
/* BIMC fabric */
#define MAS_APPS_PROC 0
#define MAS_OXILI 1
#define MAS_SNOC_BIMC_0 2
#define MAS_SNOC_BIMC_2 3
#define MAS_SNOC_BIMC_1 4
#define MAS_TCU_0 5
#define SLV_EBI 6
#define SLV_BIMC_SNOC 7
/* PCNOC fabric */
#define MAS_SPDM 0
#define MAS_BLSP_1 1
#define MAS_BLSP_2 2
#define MAS_USB_HS1 3
#define MAS_XI_USB_HS1 4
#define MAS_CRYPTO 5
#define MAS_SDCC_1 6
#define MAS_SDCC_2 7
#define MAS_SNOC_PCNOC 8
#define PCNOC_M_0 9
#define PCNOC_M_1 10
#define PCNOC_INT_0 11
#define PCNOC_INT_1 12
#define PCNOC_INT_2 13
#define PCNOC_INT_3 14
#define PCNOC_S_0 15
#define PCNOC_S_1 16
#define PCNOC_S_2 17
#define PCNOC_S_3 18
#define PCNOC_S_4 19
#define PCNOC_S_6 20
#define PCNOC_S_7 21
#define PCNOC_S_8 22
#define SLV_SDCC_2 23
#define SLV_SPDM 24
#define SLV_PDM 25
#define SLV_PRNG 26
#define SLV_TCSR 27
#define SLV_SNOC_CFG 28
#define SLV_MESSAGE_RAM 29
#define SLV_CAMERA_SS_CFG 30
#define SLV_DISP_SS_CFG 31
#define SLV_VENUS_CFG 32
#define SLV_GPU_CFG 33
#define SLV_TLMM 34
#define SLV_BLSP_1 35
#define SLV_BLSP_2 36
#define SLV_PMIC_ARB 37
#define SLV_SDCC_1 38
#define SLV_CRYPTO_0_CFG 39
#define SLV_USB_HS 40
#define SLV_TCU 41
#define SLV_PCNOC_SNOC 42
/* SNOC fabric */
#define MAS_QDSS_BAM 0
#define MAS_BIMC_SNOC 1
#define MAS_PCNOC_SNOC 2
#define MAS_QDSS_ETR 3
#define QDSS_INT 4
#define SNOC_INT_0 5
#define SNOC_INT_1 6
#define SNOC_INT_2 7
#define SLV_KPSS_AHB 8
#define SLV_WCSS 9
#define SLV_SNOC_BIMC_1 10
#define SLV_IMEM 11
#define SLV_SNOC_PCNOC 12
#define SLV_QDSS_STM 13
#define SLV_CATS_1 14
#define SLV_LPASS 15
/* SNOC-MM fabric */
#define MAS_JPEG 0
#define MAS_MDP 1
#define MAS_VENUS 2
#define MAS_VFE0 3
#define MAS_VFE1 4
#define MAS_CPP 5
#define SLV_SNOC_BIMC_0 6
#define SLV_SNOC_BIMC_2 7
#define SLV_CATS_0 8
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H */

97
include/dt-bindings/interconnect/qcom,msm8976.h Normal file
View File

@ -0,0 +1,97 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Qualcomm MSM8976 interconnect IDs
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H
/* BIMC fabric */
#define MAS_APPS_PROC 0
#define MAS_SMMNOC_BIMC 1
#define MAS_SNOC_BIMC 2
#define MAS_TCU_0 3
#define SLV_EBI 4
#define SLV_BIMC_SNOC 5
/* PCNOC fabric */
#define MAS_USB_HS2 0
#define MAS_BLSP_1 1
#define MAS_USB_HS1 2
#define MAS_BLSP_2 3
#define MAS_CRYPTO 4
#define MAS_SDCC_1 5
#define MAS_SDCC_2 6
#define MAS_SDCC_3 7
#define MAS_SNOC_PCNOC 8
#define MAS_LPASS_AHB 9
#define MAS_SPDM 10
#define MAS_DEHR 11
#define MAS_XM_USB_HS1 12
#define PCNOC_M_0 13
#define PCNOC_M_1 14
#define PCNOC_INT_0 15
#define PCNOC_INT_1 16
#define PCNOC_INT_2 17
#define PCNOC_S_1 18
#define PCNOC_S_2 19
#define PCNOC_S_3 20
#define PCNOC_S_4 21
#define PCNOC_S_8 22
#define PCNOC_S_9 23
#define SLV_TCSR 24
#define SLV_TLMM 25
#define SLV_CRYPTO_0_CFG 26
#define SLV_MESSAGE_RAM 27
#define SLV_PDM 28
#define SLV_PRNG 29
#define SLV_PMIC_ARB 30
#define SLV_SNOC_CFG 31
#define SLV_DCC_CFG 32
#define SLV_CAMERA_SS_CFG 33
#define SLV_DISP_SS_CFG 34
#define SLV_VENUS_CFG 35
#define SLV_SDCC_1 36
#define SLV_BLSP_1 37
#define SLV_USB_HS 38
#define SLV_SDCC_3 39
#define SLV_SDCC_2 40
#define SLV_GPU_CFG 41
#define SLV_USB_HS2 42
#define SLV_BLSP_2 43
#define SLV_PCNOC_SNOC 44
/* SNOC fabric */
#define MAS_QDSS_BAM 0
#define MAS_BIMC_SNOC 1
#define MAS_PCNOC_SNOC 2
#define MAS_QDSS_ETR 3
#define MAS_LPASS_PROC 4
#define MAS_IPA 5
#define QDSS_INT 6
#define SNOC_INT_0 7
#define SNOC_INT_1 8
#define SNOC_INT_2 9
#define SLV_KPSS_AHB 10
#define SLV_SNOC_BIMC 11
#define SLV_IMEM 12
#define SLV_SNOC_PCNOC 13
#define SLV_QDSS_STM 14
#define SLV_CATS_0 15
#define SLV_CATS_1 16
#define SLV_LPASS 17
/* SNOC-MM fabric */
#define MAS_JPEG 0
#define MAS_OXILI 1
#define MAS_MDP0 2
#define MAS_MDP1 3
#define MAS_VENUS_0 4
#define MAS_VENUS_1 5
#define MAS_VFE_0 6
#define MAS_VFE_1 7
#define MAS_CPP 8
#define MM_INT_0 9
#define SLV_SMMNOC_BIMC 10
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H */

10
include/dt-bindings/interconnect/qcom,sm8350.h
View File

@ -119,9 +119,6 @@
#define SLAVE_SERVICE_GEM_NOC_1 16
#define SLAVE_SERVICE_GEM_NOC_2 17
#define SLAVE_SERVICE_GEM_NOC 18
#define MASTER_MNOC_HF_MEM_NOC_DISP 19
#define MASTER_MNOC_SF_MEM_NOC_DISP 20
#define SLAVE_LLCC_DISP 21
#define MASTER_CNOC_LPASS_AG_NOC 0
#define SLAVE_LPASS_CORE_CFG 1
@ -133,8 +130,6 @@
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_LLCC_DISP 2
#define SLAVE_EBI1_DISP 3
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
@ -149,11 +144,6 @@
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_MDP0_DISP 13
#define MASTER_MDP1_DISP 14
#define MASTER_ROTATOR_DISP 15
#define SLAVE_MNOC_HF_MEM_NOC_DISP 16
#define SLAVE_MNOC_SF_MEM_NOC_DISP 17
#define MASTER_CDSP_NOC_CFG 0
#define MASTER_CDSP_PROC 1