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ASoC: meson: axg-fifo: add NO_PERIOD_WAKEUP support
On the AXG family, the fifo irq is not necessary for the HW to operate. It is just used to notify that a period has elapsed. If userpace does not care for these wakeups (such as pipewire), we are just wasting CPU cycles. Add support for NO_PERIOD_WAKEUP and disable irq when they are no needed. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210407145914.311479-1-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -27,8 +27,8 @@ static struct snd_pcm_hardware axg_fifo_hw = {
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_PAUSE),
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
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.formats = AXG_FIFO_FORMATS,
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.rate_min = 5512,
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.rate_max = 192000,
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@ -113,7 +113,7 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
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{
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struct snd_pcm_runtime *runtime = ss->runtime;
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struct axg_fifo *fifo = axg_fifo_data(ss);
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unsigned int burst_num, period, threshold;
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unsigned int burst_num, period, threshold, irq_en;
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dma_addr_t end_ptr;
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period = params_period_bytes(params);
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@ -142,10 +142,11 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
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regmap_field_write(fifo->field_threshold,
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threshold ? threshold - 1 : 0);
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/* Enable block count irq */
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/* Enable irq if necessary */
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irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
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CTRL0_INT_EN(irq_en));
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return 0;
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}
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