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ARM: OMAP4: clock data: add clockdomains for clocks used as main clocks
Until the OMAP4 code is converted to disable the use of the clock framework-based clockdomain enable/disable sequence, any clock used as a hwmod main_clk must have a clockdomain associated with it. This patch populates some clock structure clockdomain names to resolve the following warnings during kernel init: omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck. omap_hwmod: trace_clk_div_ck: missing clockdomain for trace_clk_div_ck. omap_hwmod: l3_div_ck: missing clockdomain for l3_div_ck. omap_hwmod: ddrphy_ck: missing clockdomain for ddrphy_ck. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoît Cousson <b-cousson@ti.com>
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@ -84,6 +84,7 @@ static struct clk slimbus_clk = {
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static struct clk sys_32k_ck = {
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.name = "sys_32k_ck",
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.clkdm_name = "prm_clkdm",
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.rate = 32768,
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.ops = &clkops_null,
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};
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@ -512,6 +513,7 @@ static struct clk ddrphy_ck = {
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.name = "ddrphy_ck",
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.parent = &dpll_core_m2_ck,
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.ops = &clkops_null,
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.clkdm_name = "l3_emif_clkdm",
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.fixed_div = 2,
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.recalc = &omap_fixed_divisor_recalc,
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};
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@ -769,6 +771,7 @@ static const struct clksel dpll_mpu_m2_div[] = {
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static struct clk dpll_mpu_m2_ck = {
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.name = "dpll_mpu_m2_ck",
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.parent = &dpll_mpu_ck,
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.clkdm_name = "cm_clkdm",
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.clksel = dpll_mpu_m2_div,
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.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
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.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
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@ -1149,6 +1152,7 @@ static const struct clksel l3_div_div[] = {
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static struct clk l3_div_ck = {
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.name = "l3_div_ck",
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.parent = &div_core_ck,
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.clkdm_name = "cm_clkdm",
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.clksel = l3_div_div,
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.clksel_reg = OMAP4430_CM_CLKSEL_CORE,
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.clksel_mask = OMAP4430_CLKSEL_L3_MASK,
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@ -2824,6 +2828,7 @@ static const struct clksel trace_clk_div_div[] = {
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static struct clk trace_clk_div_ck = {
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.name = "trace_clk_div_ck",
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.parent = &pmd_trace_clk_mux_ck,
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.clkdm_name = "emu_sys_clkdm",
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.clksel = trace_clk_div_div,
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.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
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.clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
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