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drm/tegra: Move drm_dp_link helpers to Tegra DRM
During the discussion of patches that enhance the drm_dp_link helpers it was concluded that these helpers aren't very useful to begin with. After all other drivers have been converted not to use these helpers anymore, move these helpers into the last remaining user: Tegra DRM. If at some point these helpers are deemed more widely useful, they can be moved out into the DRM DP helpers again. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20191021143437.1477719-14-thierry.reding@gmail.com
This commit is contained in:
Thierry Reding
parent
2589c4025f
commit
9a42c7c647
@ -351,134 +351,6 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
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}
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EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
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/**
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* drm_dp_link_probe() - probe a DisplayPort link for capabilities
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* @aux: DisplayPort AUX channel
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* @link: pointer to structure in which to return link capabilities
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*
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* The structure filled in by this function can usually be passed directly
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* into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
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* configure the link based on the link's capabilities.
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 values[3];
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int err;
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memset(link, 0, sizeof(*link));
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err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
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if (err < 0)
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return err;
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link->revision = values[0];
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link->rate = drm_dp_bw_code_to_link_rate(values[1]);
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link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
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if (values[2] & DP_ENHANCED_FRAME_CAP)
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link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_link_probe);
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/**
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* drm_dp_link_power_up() - power up a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 value;
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int err;
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/* DP_SET_POWER register is only available on DPCD v1.1 and later */
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if (link->revision < 0x11)
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return 0;
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err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
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if (err < 0)
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return err;
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value &= ~DP_SET_POWER_MASK;
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value |= DP_SET_POWER_D0;
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err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
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if (err < 0)
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return err;
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/*
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* According to the DP 1.1 specification, a "Sink Device must exit the
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* power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
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* Control Field" (register 0x600).
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*/
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usleep_range(1000, 2000);
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_link_power_up);
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/**
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* drm_dp_link_power_down() - power down a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 value;
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int err;
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/* DP_SET_POWER register is only available on DPCD v1.1 and later */
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if (link->revision < 0x11)
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return 0;
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err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
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if (err < 0)
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return err;
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value &= ~DP_SET_POWER_MASK;
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value |= DP_SET_POWER_D3;
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err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
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if (err < 0)
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return err;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_link_power_down);
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/**
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* drm_dp_link_configure() - configure a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 values[2];
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int err;
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values[0] = drm_dp_link_rate_to_bw_code(link->rate);
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values[1] = link->num_lanes;
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if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
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values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
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if (err < 0)
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return err;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_link_configure);
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/**
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* drm_dp_downstream_max_clock() - extract branch device max
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* pixel rate for legacy VGA
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@ -5,6 +5,7 @@ tegra-drm-y := \
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drm.o \
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gem.o \
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fb.o \
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dp.o \
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hub.o \
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plane.o \
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dc.o \
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133
drivers/gpu/drm/tegra/dp.c
Normal file
133
drivers/gpu/drm/tegra/dp.c
Normal file
@ -0,0 +1,133 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright (C) 2013-2019 NVIDIA Corporation
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* Copyright (C) 2015 Rob Clark
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*/
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#include <drm/drm_dp_helper.h>
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#include "dp.h"
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/**
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* drm_dp_link_probe() - probe a DisplayPort link for capabilities
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* @aux: DisplayPort AUX channel
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* @link: pointer to structure in which to return link capabilities
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*
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* The structure filled in by this function can usually be passed directly
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* into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
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* configure the link based on the link's capabilities.
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 values[3];
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int err;
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memset(link, 0, sizeof(*link));
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err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
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if (err < 0)
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return err;
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link->revision = values[0];
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link->rate = drm_dp_bw_code_to_link_rate(values[1]);
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link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
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if (values[2] & DP_ENHANCED_FRAME_CAP)
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link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
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return 0;
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}
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/**
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* drm_dp_link_power_up() - power up a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 value;
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int err;
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/* DP_SET_POWER register is only available on DPCD v1.1 and later */
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if (link->revision < 0x11)
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return 0;
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err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
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if (err < 0)
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return err;
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value &= ~DP_SET_POWER_MASK;
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value |= DP_SET_POWER_D0;
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err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
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if (err < 0)
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return err;
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/*
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* According to the DP 1.1 specification, a "Sink Device must exit the
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* power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
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* Control Field" (register 0x600).
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*/
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usleep_range(1000, 2000);
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return 0;
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}
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/**
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* drm_dp_link_power_down() - power down a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 value;
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int err;
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/* DP_SET_POWER register is only available on DPCD v1.1 and later */
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if (link->revision < 0x11)
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return 0;
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err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
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if (err < 0)
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return err;
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value &= ~DP_SET_POWER_MASK;
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value |= DP_SET_POWER_D3;
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err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
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if (err < 0)
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return err;
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return 0;
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}
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/**
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* drm_dp_link_configure() - configure a DisplayPort link
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* @aux: DisplayPort AUX channel
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* @link: pointer to a structure containing the link configuration
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
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{
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u8 values[2];
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int err;
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values[0] = drm_dp_link_rate_to_bw_code(link->rate);
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values[1] = link->num_lanes;
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if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
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values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
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if (err < 0)
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return err;
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return 0;
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}
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26
drivers/gpu/drm/tegra/dp.h
Normal file
26
drivers/gpu/drm/tegra/dp.h
Normal file
@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2013-2019 NVIDIA Corporation.
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* Copyright (C) 2015 Rob Clark
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*/
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#ifndef DRM_TEGRA_DP_H
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#define DRM_TEGRA_DP_H 1
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struct drm_dp_aux;
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#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
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struct drm_dp_link {
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unsigned char revision;
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unsigned int rate;
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unsigned int num_lanes;
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unsigned long capabilities;
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};
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
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#endif
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@ -22,6 +22,7 @@
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include "dp.h"
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#include "dpaux.h"
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#include "drm.h"
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#include "trace.h"
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@ -25,6 +25,7 @@
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#include <drm/drm_scdc_helper.h>
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#include "dc.h"
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#include "dp.h"
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#include "drm.h"
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#include "hda.h"
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#include "sor.h"
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@ -1455,22 +1455,6 @@ static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
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int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
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u8 status[DP_LINK_STATUS_SIZE]);
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/*
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* DisplayPort link
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*/
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#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
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struct drm_dp_link {
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unsigned char revision;
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unsigned int rate;
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unsigned int num_lanes;
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unsigned long capabilities;
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};
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
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const u8 port_cap[4]);
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int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
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