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ath9k_hw: Update AR9485 initvals to fix system hang issue
This patch fixes system hang when resuming from S3 state and lower rate sens failure issue. Cc: stable@kernel.org Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -521,7 +521,7 @@ static const u32 ar9485_1_1_radio_postamble[][2] = {
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{0x000160ac, 0x24611800},
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{0x000160b0, 0x03284f3e},
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{0x0001610c, 0x00170000},
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{0x00016140, 0x10804008},
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{0x00016140, 0x50804008},
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};
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static const u32 ar9485_1_1_mac_postamble[][5] = {
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@ -603,7 +603,7 @@ static const u32 ar9485_1_1_radio_core[][2] = {
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static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x10052e5e},
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{0x00018c00, 0x18052e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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@ -776,7 +776,7 @@ static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
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static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x10013e5e},
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{0x00018c00, 0x18013e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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@ -882,7 +882,7 @@ static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
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static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x10012e5e},
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{0x00018c00, 0x18012e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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@ -1021,7 +1021,7 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
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static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x10053e5e},
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{0x00018c00, 0x18053e5e},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0000080c},
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};
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