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oprofile/x86: warn user if a counter is already active
This patch generates a warning if a counter is already active. Implemented for AMD and P6 models. P4 is not supported. Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: Robert Richter <robert.richter@amd.com>
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@ -194,9 +194,18 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* clear all counters */
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for (i = 0; i < NUM_CONTROLS; ++i) {
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if (unlikely(!msrs->controls[i].addr))
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if (unlikely(!msrs->controls[i].addr)) {
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if (counter_config[i].enabled && !smp_processor_id())
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/*
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* counter is reserved, this is on all
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* cpus, so report only for cpu #0
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*/
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op_x86_warn_reserved(i);
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continue;
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}
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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@ -82,9 +82,18 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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/* clear all counters */
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for (i = 0; i < num_counters; ++i) {
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if (unlikely(!msrs->controls[i].addr))
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if (unlikely(!msrs->controls[i].addr)) {
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if (counter_config[i].enabled && !smp_processor_id())
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/*
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* counter is reserved, this is on all
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* cpus, so report only for cpu #0
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*/
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op_x86_warn_reserved(i);
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continue;
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}
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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@ -57,6 +57,17 @@ struct op_x86_model_spec {
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struct op_counter_config;
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static inline void op_x86_warn_in_use(int counter)
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{
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pr_warning("oprofile: counter #%d on cpu #%d may already be used\n",
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counter, smp_processor_id());
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}
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static inline void op_x86_warn_reserved(int counter)
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{
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pr_warning("oprofile: counter #%d is already reserved\n", counter);
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}
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extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
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struct op_counter_config *counter_config);
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extern int op_x86_phys_to_virt(int phys);
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