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phy: ralink: phy-mt7621-pci: fix XTAL bitmask

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When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.

Fixes: d87da32372 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sergio Paracuellos 2021-03-02 11:54:12 +01:00 committed by Vinod Koul
parent ed9e07f815
commit 982313c38f
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/ralink/phy-mt7621-pci.c
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@ -62,7 +62,7 @@
#define RG_PE1_FRC_MSTCKDIV BIT(5)
#define XTAL_MASK GENMASK(7, 6)
#define XTAL_MASK GENMASK(8, 6)
#define MAX_PHYS 2