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phy: brcm-sata: Implement 7216 initialization sequence
7216 is a 16nm process chip with a slightly different version of the PHY SerdDeS/AFE that requires a specific tuning sequence. Key on the compatible string to perform that initialization. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Florian Fainelli
Kishon Vijay Abraham I
parent
d0c05c68d6
commit
978442532e
@ -33,6 +33,7 @@
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#define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
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enum brcm_sata_phy_version {
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BRCM_SATA_PHY_STB_16NM,
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BRCM_SATA_PHY_STB_28NM,
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BRCM_SATA_PHY_STB_40NM,
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BRCM_SATA_PHY_IPROC_NS2,
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@ -104,10 +105,13 @@ enum sata_phy_regs {
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PLL1_ACTRL5 = 0x85,
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PLL1_ACTRL6 = 0x86,
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PLL1_ACTRL7 = 0x87,
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PLL1_ACTRL8 = 0x88,
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TX_REG_BANK = 0x070,
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TX_ACTRL0 = 0x80,
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TX_ACTRL0_TXPOL_FLIP = BIT(6),
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TX_ACTRL5 = 0x85,
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TX_ACTRL5_SSC_EN = BIT(11),
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AEQRX_REG_BANK_0 = 0xd0,
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AEQ_CONTROL1 = 0x81,
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@ -116,6 +120,7 @@ enum sata_phy_regs {
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AEQ_FRC_EQ = 0x83,
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AEQ_FRC_EQ_FORCE = BIT(0),
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AEQ_FRC_EQ_FORCE_VAL = BIT(1),
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AEQ_RFZ_FRC_VAL = BIT(8),
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AEQRX_REG_BANK_1 = 0xe0,
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AEQRX_SLCAL0_CTRL0 = 0x82,
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AEQRX_SLCAL1_CTRL0 = 0x86,
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@ -152,7 +157,28 @@ enum sata_phy_regs {
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TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
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RXPMD_REG_BANK = 0x1c0,
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RXPMD_RX_CDR_CONTROL1 = 0x81,
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RXPMD_RX_PPM_VAL_MASK = 0x1ff,
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RXPMD_RXPMD_EN_FRC = BIT(12),
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RXPMD_RXPMD_EN_FRC_VAL = BIT(13),
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RXPMD_RX_CDR_CDR_PROP_BW = 0x82,
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RXPMD_G_CDR_PROP_BW_MASK = 0x7,
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RXPMD_G1_CDR_PROP_BW_SHIFT = 0,
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RXPMD_G2_CDR_PROP_BW_SHIFT = 3,
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RXPMD_G3_CDR_PROB_BW_SHIFT = 6,
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RXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 0x83,
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RXPMD_G_CDR_ACQ_INT_BW_MASK = 0x7,
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RXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,
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RXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,
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RXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,
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RXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 0x84,
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RXPMD_G_CDR_LOCK_INT_BW_MASK = 0x7,
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RXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,
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RXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,
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RXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,
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RXPMD_RX_FREQ_MON_CONTROL1 = 0x87,
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RXPMD_MON_CORRECT_EN = BIT(8),
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RXPMD_MON_MARGIN_VAL_MASK = 0xff,
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};
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enum sata_phy_ctrl_regs {
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@ -166,6 +192,7 @@ static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
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u32 size = 0;
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switch (priv->version) {
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case BRCM_SATA_PHY_STB_16NM:
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_IPROC_NS2:
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case BRCM_SATA_PHY_DSL_28NM:
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@ -287,6 +314,94 @@ static int brcm_stb_sata_init(struct brcm_sata_port *port)
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return brcm_stb_sata_rxaeq_init(port);
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}
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static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_pcb_base(port);
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u32 tmp, value;
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/* Reduce CP tail current to 1/16th of its default value */
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
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/* Turn off CP tail current boost */
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
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/* Set a specific AEQ equalizer value */
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tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
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brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
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~(tmp | AEQ_RFZ_FRC_VAL |
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AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
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tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
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/* Set RX PPM val center frequency */
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if (port->ssc_en)
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value = 0x52;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
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~RXPMD_RX_PPM_VAL_MASK, value);
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/* Set proportional loop bandwith Gen1/2/3 */
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tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
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RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
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RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
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if (port->ssc_en)
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value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
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2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
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2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
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else
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value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
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1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
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1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
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value);
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/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
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tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
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RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
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RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
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if (port->ssc_en)
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value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
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1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
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1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
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~tmp, value);
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/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
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tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
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RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
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RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
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if (port->ssc_en)
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value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
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1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
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1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
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~tmp, value);
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/* Set no guard band and clamp CDR */
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tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
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if (port->ssc_en)
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value = 0x51;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
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~tmp, RXPMD_MON_CORRECT_EN | value);
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/* Turn on/off SSC */
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brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
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port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
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return 0;
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}
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static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
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{
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return brcm_stb_sata_16nm_ssc_init(port);
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}
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/* NS2 SATA PLL1 defaults were characterized by H/W group */
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#define NS2_PLL1_ACTRL2_MAGIC 0x1df8
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#define NS2_PLL1_ACTRL3_MAGIC 0x2b00
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@ -544,6 +659,9 @@ static int brcm_sata_phy_init(struct phy *phy)
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struct brcm_sata_port *port = phy_get_drvdata(phy);
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switch (port->phy_priv->version) {
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case BRCM_SATA_PHY_STB_16NM:
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rc = brcm_stb_sata_16nm_init(port);
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break;
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_STB_40NM:
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rc = brcm_stb_sata_init(port);
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@ -601,6 +719,8 @@ static const struct phy_ops phy_ops = {
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};
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static const struct of_device_id brcm_sata_phy_of_match[] = {
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{ .compatible = "brcm,bcm7216-sata-phy",
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.data = (void *)BRCM_SATA_PHY_STB_16NM },
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{ .compatible = "brcm,bcm7445-sata-phy",
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.data = (void *)BRCM_SATA_PHY_STB_28NM },
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{ .compatible = "brcm,bcm7425-sata-phy",
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