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watchdog: qcom: fine tune the max timeout value calculation

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To determine the max_timeout value, the below calculation is used.

	max_timeout = 0x10000000 / clk_rate

cat /sys/devices/platform/soc@0/b017000.watchdog/watchdog/watchdog0/max_timeout
8388

However, this is not valid for all the platforms. IPQ SoCs starting from
IPQ40xx and recent Snapdragron SoCs also has the bark and bite time field
length of 20bits, which can hold max up to 32 seconds if the clk_rate is
32KHz.

If the user tries to configure the timeout more than 32s, then the value
will be truncated and the actual value will not be reflected in the HW.

To avoid this, lets add a variable called max_tick_count in the device data,
which defines max counter value of the WDT controller. Using this, max-timeout
will be calculated in runtime for various WDT contorllers.

With this change, we get the proper max_timeout as below and restricts
the user from configuring the timeout higher than this.

cat /sys/devices/platform/soc@0/b017000.watchdog/watchdog/watchdog0/max_timeout
32

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20240116-wdt-v2-1-501c7694c3f0@quicinc.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Kathiravan Thirumoorthy 2024-01-16 13:52:43 +05:30 committed by Wim Van Sebroeck
parent d2f656dc49
commit 975e4b273e
1 changed files with 5 additions and 2 deletions
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7
drivers/watchdog/qcom-wdt.c
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@ -41,6 +41,7 @@ static const u32 reg_offset_data_kpss[] = {
struct qcom_wdt_match_data { struct qcom_wdt_match_data {
const u32 *offset; const u32 *offset;
bool pretimeout; bool pretimeout;
u32 max_tick_count;
}; };
struct qcom_wdt { struct qcom_wdt {
@ -177,11 +178,13 @@ static const struct watchdog_info qcom_wdt_pt_info = {
static const struct qcom_wdt_match_data match_data_apcs_tmr = { static const struct qcom_wdt_match_data match_data_apcs_tmr = {
.offset = reg_offset_data_apcs_tmr, .offset = reg_offset_data_apcs_tmr,
.pretimeout = false, .pretimeout = false,
.max_tick_count = 0x10000000U,
}; };
static const struct qcom_wdt_match_data match_data_kpss = { static const struct qcom_wdt_match_data match_data_kpss = {
.offset = reg_offset_data_kpss, .offset = reg_offset_data_kpss,
.pretimeout = true, .pretimeout = true,
.max_tick_count = 0xFFFFFU,
}; };
static int qcom_wdt_probe(struct platform_device *pdev) static int qcom_wdt_probe(struct platform_device *pdev)
@ -236,7 +239,7 @@ static int qcom_wdt_probe(struct platform_device *pdev)
*/ */
wdt->rate = clk_get_rate(clk); wdt->rate = clk_get_rate(clk);
if (wdt->rate == 0 || if (wdt->rate == 0 ||
wdt->rate > 0x10000000U) { wdt->rate > data->max_tick_count) {
dev_err(dev, "invalid clock rate\n"); dev_err(dev, "invalid clock rate\n");
return -EINVAL; return -EINVAL;
} }
@ -260,7 +263,7 @@ static int qcom_wdt_probe(struct platform_device *pdev)
wdt->wdd.ops = &qcom_wdt_ops; wdt->wdd.ops = &qcom_wdt_ops;
wdt->wdd.min_timeout = 1; wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = 0x10000000U / wdt->rate; wdt->wdd.max_timeout = data->max_tick_count / wdt->rate;
wdt->wdd.parent = dev; wdt->wdd.parent = dev;
wdt->layout = data->offset; wdt->layout = data->offset;