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drm/nva3/copy: update fuc source for latest envytools
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
d2491567cd
commit
971fa6b46d
@ -31,8 +31,9 @@
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*/
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*/
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ifdef(`NVA3',
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ifdef(`NVA3',
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.section nva3_pcopy_data,
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.section #nva3_pcopy_data
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.section nvc0_pcopy_data
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,
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.section #nvc0_pcopy_data
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)
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)
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ctx_object: .b32 0
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ctx_object: .b32 0
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@ -42,7 +43,7 @@ ctx_dma_query: .b32 0
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ctx_dma_src: .b32 0
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ctx_dma_src: .b32 0
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ctx_dma_dst: .b32 0
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ctx_dma_dst: .b32 0
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,)
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,)
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.equ ctx_dma_count 3
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.equ #ctx_dma_count 3
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ctx_query_address_high: .b32 0
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ctx_query_address_high: .b32 0
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ctx_query_address_low: .b32 0
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ctx_query_address_low: .b32 0
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ctx_query_counter: .b32 0
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ctx_query_counter: .b32 0
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@ -78,64 +79,65 @@ ctx_ycnt: .b32 0
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dispatch_table:
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dispatch_table:
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// mthd 0x0000, NAME
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// mthd 0x0000, NAME
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.b16 0x000 1
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.b16 0x000 1
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.b32 ctx_object ~0xffffffff
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.b32 #ctx_object ~0xffffffff
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// mthd 0x0100, NOP
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// mthd 0x0100, NOP
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.b16 0x040 1
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.b16 0x040 1
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.b32 0x00010000 + cmd_nop ~0xffffffff
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.b32 0x00010000 + #cmd_nop ~0xffffffff
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// mthd 0x0140, PM_TRIGGER
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// mthd 0x0140, PM_TRIGGER
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.b16 0x050 1
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.b16 0x050 1
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.b32 0x00010000 + cmd_pm_trigger ~0xffffffff
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.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff
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ifdef(`NVA3', `
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ifdef(`NVA3', `
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// mthd 0x0180-0x018c, DMA_
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// mthd 0x0180-0x018c, DMA_
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.b16 0x060 ctx_dma_count
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.b16 0x060 #ctx_dma_count
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dispatch_dma:
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dispatch_dma:
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.b32 0x00010000 + cmd_dma ~0xffffffff
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.b32 0x00010000 + #cmd_dma ~0xffffffff
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.b32 0x00010000 + cmd_dma ~0xffffffff
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.b32 0x00010000 + #cmd_dma ~0xffffffff
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.b32 0x00010000 + cmd_dma ~0xffffffff
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.b32 0x00010000 + #cmd_dma ~0xffffffff
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',)
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',)
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// mthd 0x0200-0x0218, SRC_TILE
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// mthd 0x0200-0x0218, SRC_TILE
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.b16 0x80 7
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.b16 0x80 7
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.b32 ctx_src_tile_mode ~0x00000fff
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.b32 #ctx_src_tile_mode ~0x00000fff
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.b32 ctx_src_xsize ~0x0007ffff
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.b32 #ctx_src_xsize ~0x0007ffff
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.b32 ctx_src_ysize ~0x00001fff
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.b32 #ctx_src_ysize ~0x00001fff
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.b32 ctx_src_zsize ~0x000007ff
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.b32 #ctx_src_zsize ~0x000007ff
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.b32 ctx_src_zoff ~0x00000fff
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.b32 #ctx_src_zoff ~0x00000fff
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.b32 ctx_src_xoff ~0x0007ffff
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.b32 #ctx_src_xoff ~0x0007ffff
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.b32 ctx_src_yoff ~0x00001fff
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.b32 #ctx_src_yoff ~0x00001fff
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// mthd 0x0220-0x0238, DST_TILE
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// mthd 0x0220-0x0238, DST_TILE
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.b16 0x88 7
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.b16 0x88 7
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.b32 ctx_dst_tile_mode ~0x00000fff
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.b32 #ctx_dst_tile_mode ~0x00000fff
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.b32 ctx_dst_xsize ~0x0007ffff
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.b32 #ctx_dst_xsize ~0x0007ffff
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.b32 ctx_dst_ysize ~0x00001fff
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.b32 #ctx_dst_ysize ~0x00001fff
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.b32 ctx_dst_zsize ~0x000007ff
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.b32 #ctx_dst_zsize ~0x000007ff
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.b32 ctx_dst_zoff ~0x00000fff
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.b32 #ctx_dst_zoff ~0x00000fff
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.b32 ctx_dst_xoff ~0x0007ffff
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.b32 #ctx_dst_xoff ~0x0007ffff
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.b32 ctx_dst_yoff ~0x00001fff
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.b32 #ctx_dst_yoff ~0x00001fff
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// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
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// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
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.b16 0xc0 2
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.b16 0xc0 2
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.b32 0x00010000 + cmd_exec ~0xffffffff
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.b32 0x00010000 + #cmd_exec ~0xffffffff
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.b32 0x00010000 + cmd_wrcache_flush ~0xffffffff
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.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff
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// mthd 0x030c-0x0340, various stuff
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// mthd 0x030c-0x0340, various stuff
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.b16 0xc3 14
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.b16 0xc3 14
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.b32 ctx_src_address_high ~0x000000ff
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.b32 #ctx_src_address_high ~0x000000ff
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.b32 ctx_src_address_low ~0xfffffff0
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.b32 #ctx_src_address_low ~0xfffffff0
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.b32 ctx_dst_address_high ~0x000000ff
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.b32 #ctx_dst_address_high ~0x000000ff
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.b32 ctx_dst_address_low ~0xfffffff0
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.b32 #ctx_dst_address_low ~0xfffffff0
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.b32 ctx_src_pitch ~0x0007ffff
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.b32 #ctx_src_pitch ~0x0007ffff
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.b32 ctx_dst_pitch ~0x0007ffff
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.b32 #ctx_dst_pitch ~0x0007ffff
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.b32 ctx_xcnt ~0x0000ffff
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.b32 #ctx_xcnt ~0x0000ffff
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.b32 ctx_ycnt ~0x00001fff
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.b32 #ctx_ycnt ~0x00001fff
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.b32 ctx_format ~0x0333ffff
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.b32 #ctx_format ~0x0333ffff
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.b32 ctx_swz_const0 ~0xffffffff
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.b32 #ctx_swz_const0 ~0xffffffff
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.b32 ctx_swz_const1 ~0xffffffff
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.b32 #ctx_swz_const1 ~0xffffffff
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.b32 ctx_query_address_high ~0x000000ff
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.b32 #ctx_query_address_high ~0x000000ff
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.b32 ctx_query_address_low ~0xffffffff
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.b32 #ctx_query_address_low ~0xffffffff
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.b32 ctx_query_counter ~0xffffffff
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.b32 #ctx_query_counter ~0xffffffff
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.b16 0x800 0
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.b16 0x800 0
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ifdef(`NVA3',
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ifdef(`NVA3',
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.section nva3_pcopy_code,
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.section #nva3_pcopy_code
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.section nvc0_pcopy_code
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,
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.section #nvc0_pcopy_code
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)
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)
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main:
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main:
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@ -143,7 +145,7 @@ main:
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mov $sp $r0
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mov $sp $r0
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// setup i0 handler and route fifo and ctxswitch to it
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// setup i0 handler and route fifo and ctxswitch to it
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mov $r1 ih
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mov $r1 #ih
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mov $iv0 $r1
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mov $iv0 $r1
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mov $r1 0x400
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mov $r1 0x400
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movw $r2 0xfff3
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movw $r2 0xfff3
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@ -164,19 +166,19 @@ main:
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bset $flags $p0
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bset $flags $p0
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spin:
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spin:
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sleep $p0
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sleep $p0
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bra spin
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bra #spin
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// i0 handler
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// i0 handler
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ih:
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ih:
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iord $r1 I[$r0 + 0x200]
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iord $r1 I[$r0 + 0x200]
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and $r2 $r1 0x00000008
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and $r2 $r1 0x00000008
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bra e ih_no_chsw
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bra e #ih_no_chsw
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call chsw
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call #chsw
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ih_no_chsw:
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ih_no_chsw:
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and $r2 $r1 0x00000004
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and $r2 $r1 0x00000004
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bra e ih_no_cmd
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bra e #ih_no_cmd
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call dispatch
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call #dispatch
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ih_no_cmd:
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ih_no_cmd:
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and $r1 $r1 0x0000000c
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and $r1 $r1 0x0000000c
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@ -235,9 +237,9 @@ ifdef(`NVA3', `
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sethi $r4 0x60000
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sethi $r4 0x60000
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// swap!
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// swap!
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bra $p1 swctx_load
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bra $p1 #swctx_load
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xdst $r0 $r4
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xdst $r0 $r4
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bra swctx_done
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bra #swctx_done
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swctx_load:
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swctx_load:
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xdld $r0 $r4
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xdld $r0 $r4
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swctx_done:
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swctx_done:
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@ -251,9 +253,9 @@ chsw:
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// if it's active, unload it and return
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// if it's active, unload it and return
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xbit $r15 $r3 0x1e
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xbit $r15 $r3 0x1e
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bra e chsw_no_unload
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bra e #chsw_no_unload
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bclr $flags $p1
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bclr $flags $p1
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call swctx
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call #swctx
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bclr $r3 0x1e
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bclr $r3 0x1e
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iowr I[$r2] $r3
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iowr I[$r2] $r3
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mov $r4 1
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mov $r4 1
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@ -266,20 +268,20 @@ chsw:
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// is there a channel waiting to be loaded?
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// is there a channel waiting to be loaded?
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xbit $r13 $r3 0x1e
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xbit $r13 $r3 0x1e
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bra e chsw_finish_load
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bra e #chsw_finish_load
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bset $flags $p1
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bset $flags $p1
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call swctx
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call #swctx
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ifdef(`NVA3',
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ifdef(`NVA3',
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// load dma objects back into TARGET regs
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// load dma objects back into TARGET regs
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mov $r5 ctx_dma
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mov $r5 #ctx_dma
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mov $r6 ctx_dma_count
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mov $r6 #ctx_dma_count
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chsw_load_ctx_dma:
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chsw_load_ctx_dma:
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ld b32 $r7 D[$r5 + $r6 * 4]
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ld b32 $r7 D[$r5 + $r6 * 4]
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add b32 $r8 $r6 0x180
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add b32 $r8 $r6 0x180
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shl b32 $r8 8
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shl b32 $r8 8
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iowr I[$r8] $r7
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iowr I[$r8] $r7
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sub b32 $r6 1
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sub b32 $r6 1
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bra nc chsw_load_ctx_dma
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bra nc #chsw_load_ctx_dma
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,)
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,)
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chsw_finish_load:
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chsw_finish_load:
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@ -297,7 +299,7 @@ dispatch:
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shl b32 $r2 0x10
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shl b32 $r2 0x10
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// lookup method in the dispatch table, ILLEGAL_MTHD if not found
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// lookup method in the dispatch table, ILLEGAL_MTHD if not found
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mov $r5 dispatch_table
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mov $r5 #dispatch_table
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clear b32 $r6
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clear b32 $r6
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clear b32 $r7
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clear b32 $r7
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dispatch_loop:
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dispatch_loop:
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@ -305,14 +307,14 @@ dispatch:
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ld b16 $r7 D[$r5 + 2]
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ld b16 $r7 D[$r5 + 2]
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add b32 $r5 4
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add b32 $r5 4
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cmpu b32 $r4 $r6
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cmpu b32 $r4 $r6
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bra c dispatch_illegal_mthd
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bra c #dispatch_illegal_mthd
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add b32 $r7 $r6
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add b32 $r7 $r6
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cmpu b32 $r4 $r7
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cmpu b32 $r4 $r7
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bra c dispatch_valid_mthd
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bra c #dispatch_valid_mthd
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sub b32 $r7 $r6
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sub b32 $r7 $r6
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shl b32 $r7 3
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shl b32 $r7 3
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add b32 $r5 $r7
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add b32 $r5 $r7
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bra dispatch_loop
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bra #dispatch_loop
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// ensure no bits set in reserved fields, INVALID_BITFIELD
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// ensure no bits set in reserved fields, INVALID_BITFIELD
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dispatch_valid_mthd:
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dispatch_valid_mthd:
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@ -322,20 +324,20 @@ dispatch:
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ld b32 $r5 D[$r4 + 4]
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ld b32 $r5 D[$r4 + 4]
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and $r5 $r3
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and $r5 $r3
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cmpu b32 $r5 0
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cmpu b32 $r5 0
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bra ne dispatch_invalid_bitfield
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bra ne #dispatch_invalid_bitfield
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// depending on dispatch flags: execute method, or save data as state
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// depending on dispatch flags: execute method, or save data as state
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ld b16 $r5 D[$r4 + 0]
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ld b16 $r5 D[$r4 + 0]
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ld b16 $r6 D[$r4 + 2]
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ld b16 $r6 D[$r4 + 2]
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cmpu b32 $r6 0
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cmpu b32 $r6 0
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bra ne dispatch_cmd
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bra ne #dispatch_cmd
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st b32 D[$r5] $r3
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st b32 D[$r5] $r3
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bra dispatch_done
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bra #dispatch_done
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dispatch_cmd:
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dispatch_cmd:
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bclr $flags $p1
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bclr $flags $p1
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call $r5
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call $r5
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bra $p1 dispatch_error
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bra $p1 #dispatch_error
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bra dispatch_done
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bra #dispatch_done
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dispatch_invalid_bitfield:
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dispatch_invalid_bitfield:
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or $r2 2
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or $r2 2
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@ -353,7 +355,7 @@ dispatch:
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iord $r2 I[$r0 + 0x200]
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iord $r2 I[$r0 + 0x200]
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and $r2 0x40
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and $r2 0x40
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cmpu b32 $r2 0
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cmpu b32 $r2 0
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bra ne hostirq_wait
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bra ne #hostirq_wait
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dispatch_done:
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dispatch_done:
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mov $r2 0x1d00
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mov $r2 0x1d00
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@ -409,10 +411,10 @@ ifdef(`NVA3',
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// $r2: hostirq state
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// $r2: hostirq state
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// $r3: data
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// $r3: data
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cmd_dma:
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cmd_dma:
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sub b32 $r4 dispatch_dma
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sub b32 $r4 #dispatch_dma
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shr b32 $r4 1
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shr b32 $r4 1
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bset $r3 0x1e
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bset $r3 0x1e
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st b32 D[$r4 + ctx_dma] $r3
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st b32 D[$r4 + #ctx_dma] $r3
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add b32 $r4 0x600
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add b32 $r4 0x600
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shl b32 $r4 6
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shl b32 $r4 6
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iowr I[$r4] $r3
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iowr I[$r4] $r3
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@ -430,7 +432,7 @@ cmd_exec_set_format:
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st b32 D[$sp + 0x0c] $r0
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st b32 D[$sp + 0x0c] $r0
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// extract cpp, src_ncomp and dst_ncomp from FORMAT
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// extract cpp, src_ncomp and dst_ncomp from FORMAT
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ld b32 $r4 D[$r0 + ctx_format]
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ld b32 $r4 D[$r0 + #ctx_format]
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extr $r5 $r4 16:17
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extr $r5 $r4 16:17
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add b32 $r5 1
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add b32 $r5 1
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extr $r6 $r4 20:21
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extr $r6 $r4 20:21
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@ -448,22 +450,22 @@ cmd_exec_set_format:
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clear b32 $r11
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clear b32 $r11
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bpc_loop:
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bpc_loop:
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cmpu b8 $r10 4
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cmpu b8 $r10 4
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bra nc cmp_c0
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bra nc #cmp_c0
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mulu $r12 $r10 $r5
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mulu $r12 $r10 $r5
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add b32 $r12 $r11
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add b32 $r12 $r11
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bset $flags $p2
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bset $flags $p2
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bra bpc_next
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bra #bpc_next
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cmp_c0:
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cmp_c0:
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bra ne cmp_c1
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bra ne #cmp_c1
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mov $r12 0x10
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mov $r12 0x10
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add b32 $r12 $r11
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add b32 $r12 $r11
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bra bpc_next
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bra #bpc_next
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cmp_c1:
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cmp_c1:
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cmpu b8 $r10 6
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cmpu b8 $r10 6
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bra nc cmp_zero
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bra nc #cmp_zero
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mov $r12 0x14
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mov $r12 0x14
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add b32 $r12 $r11
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add b32 $r12 $r11
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bra bpc_next
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bra #bpc_next
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cmp_zero:
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cmp_zero:
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mov $r12 0x80
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mov $r12 0x80
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bpc_next:
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bpc_next:
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@ -471,22 +473,22 @@ cmd_exec_set_format:
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add b32 $r8 1
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add b32 $r8 1
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add b32 $r11 1
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add b32 $r11 1
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cmpu b32 $r11 $r5
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cmpu b32 $r11 $r5
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bra c bpc_loop
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bra c #bpc_loop
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add b32 $r9 1
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add b32 $r9 1
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cmpu b32 $r9 $r7
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cmpu b32 $r9 $r7
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bra c ncomp_loop
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bra c #ncomp_loop
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// SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
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// SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
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mulu $r6 $r5
|
mulu $r6 $r5
|
||||||
st b32 D[$r0 + ctx_src_cpp] $r6
|
st b32 D[$r0 + #ctx_src_cpp] $r6
|
||||||
ld b32 $r8 D[$r0 + ctx_xcnt]
|
ld b32 $r8 D[$r0 + #ctx_xcnt]
|
||||||
mulu $r6 $r8
|
mulu $r6 $r8
|
||||||
bra $p2 dst_xcnt
|
bra $p2 #dst_xcnt
|
||||||
clear b32 $r6
|
clear b32 $r6
|
||||||
|
|
||||||
dst_xcnt:
|
dst_xcnt:
|
||||||
mulu $r7 $r5
|
mulu $r7 $r5
|
||||||
st b32 D[$r0 + ctx_dst_cpp] $r7
|
st b32 D[$r0 + #ctx_dst_cpp] $r7
|
||||||
mulu $r7 $r8
|
mulu $r7 $r8
|
||||||
|
|
||||||
mov $r5 0x810
|
mov $r5 0x810
|
||||||
@ -494,10 +496,10 @@ cmd_exec_set_format:
|
|||||||
iowr I[$r5 + 0x000] $r6
|
iowr I[$r5 + 0x000] $r6
|
||||||
iowr I[$r5 + 0x100] $r7
|
iowr I[$r5 + 0x100] $r7
|
||||||
add b32 $r5 0x800
|
add b32 $r5 0x800
|
||||||
ld b32 $r6 D[$r0 + ctx_dst_cpp]
|
ld b32 $r6 D[$r0 + #ctx_dst_cpp]
|
||||||
sub b32 $r6 1
|
sub b32 $r6 1
|
||||||
shl b32 $r6 8
|
shl b32 $r6 8
|
||||||
ld b32 $r7 D[$r0 + ctx_src_cpp]
|
ld b32 $r7 D[$r0 + #ctx_src_cpp]
|
||||||
sub b32 $r7 1
|
sub b32 $r7 1
|
||||||
or $r6 $r7
|
or $r6 $r7
|
||||||
iowr I[$r5 + 0x000] $r6
|
iowr I[$r5 + 0x000] $r6
|
||||||
@ -511,9 +513,9 @@ cmd_exec_set_format:
|
|||||||
ld b32 $r6 D[$sp + 0x0c]
|
ld b32 $r6 D[$sp + 0x0c]
|
||||||
iowr I[$r5 + 0x300] $r6
|
iowr I[$r5 + 0x300] $r6
|
||||||
add b32 $r5 0x400
|
add b32 $r5 0x400
|
||||||
ld b32 $r6 D[$r0 + ctx_swz_const0]
|
ld b32 $r6 D[$r0 + #ctx_swz_const0]
|
||||||
iowr I[$r5 + 0x000] $r6
|
iowr I[$r5 + 0x000] $r6
|
||||||
ld b32 $r6 D[$r0 + ctx_swz_const1]
|
ld b32 $r6 D[$r0 + #ctx_swz_const1]
|
||||||
iowr I[$r5 + 0x100] $r6
|
iowr I[$r5 + 0x100] $r6
|
||||||
add $sp 0x10
|
add $sp 0x10
|
||||||
ret
|
ret
|
||||||
@ -543,7 +545,7 @@ cmd_exec_set_format:
|
|||||||
//
|
//
|
||||||
cmd_exec_set_surface_tiled:
|
cmd_exec_set_surface_tiled:
|
||||||
// translate TILE_MODE into Tp, Th, Td shift values
|
// translate TILE_MODE into Tp, Th, Td shift values
|
||||||
ld b32 $r7 D[$r5 + ctx_src_tile_mode]
|
ld b32 $r7 D[$r5 + #ctx_src_tile_mode]
|
||||||
extr $r9 $r7 8:11
|
extr $r9 $r7 8:11
|
||||||
extr $r8 $r7 4:7
|
extr $r8 $r7 4:7
|
||||||
ifdef(`NVA3',
|
ifdef(`NVA3',
|
||||||
@ -553,9 +555,9 @@ ifdef(`NVA3',
|
|||||||
)
|
)
|
||||||
extr $r7 $r7 0:3
|
extr $r7 $r7 0:3
|
||||||
cmp b32 $r7 0xe
|
cmp b32 $r7 0xe
|
||||||
bra ne xtile64
|
bra ne #xtile64
|
||||||
mov $r7 4
|
mov $r7 4
|
||||||
bra xtileok
|
bra #xtileok
|
||||||
xtile64:
|
xtile64:
|
||||||
xbit $r7 $flags $p2
|
xbit $r7 $flags $p2
|
||||||
add b32 $r7 17
|
add b32 $r7 17
|
||||||
@ -565,8 +567,8 @@ ifdef(`NVA3',
|
|||||||
|
|
||||||
// Op = (x * cpp) & ((1 << Tp) - 1)
|
// Op = (x * cpp) & ((1 << Tp) - 1)
|
||||||
// Tx = (x * cpp) >> Tp
|
// Tx = (x * cpp) >> Tp
|
||||||
ld b32 $r10 D[$r5 + ctx_src_xoff]
|
ld b32 $r10 D[$r5 + #ctx_src_xoff]
|
||||||
ld b32 $r11 D[$r5 + ctx_src_cpp]
|
ld b32 $r11 D[$r5 + #ctx_src_cpp]
|
||||||
mulu $r10 $r11
|
mulu $r10 $r11
|
||||||
mov $r11 1
|
mov $r11 1
|
||||||
shl b32 $r11 $r7
|
shl b32 $r11 $r7
|
||||||
@ -576,7 +578,7 @@ ifdef(`NVA3',
|
|||||||
|
|
||||||
// Tyo = y & ((1 << Th) - 1)
|
// Tyo = y & ((1 << Th) - 1)
|
||||||
// Ty = y >> Th
|
// Ty = y >> Th
|
||||||
ld b32 $r13 D[$r5 + ctx_src_yoff]
|
ld b32 $r13 D[$r5 + #ctx_src_yoff]
|
||||||
mov $r14 1
|
mov $r14 1
|
||||||
shl b32 $r14 $r8
|
shl b32 $r14 $r8
|
||||||
sub b32 $r14 1
|
sub b32 $r14 1
|
||||||
@ -598,8 +600,8 @@ ifdef(`NVA3',
|
|||||||
add b32 $r12 $r11
|
add b32 $r12 $r11
|
||||||
|
|
||||||
// nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
|
// nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
|
||||||
ld b32 $r15 D[$r5 + ctx_src_xsize]
|
ld b32 $r15 D[$r5 + #ctx_src_xsize]
|
||||||
ld b32 $r11 D[$r5 + ctx_src_cpp]
|
ld b32 $r11 D[$r5 + #ctx_src_cpp]
|
||||||
mulu $r15 $r11
|
mulu $r15 $r11
|
||||||
mov $r11 1
|
mov $r11 1
|
||||||
shl b32 $r11 $r7
|
shl b32 $r11 $r7
|
||||||
@ -609,7 +611,7 @@ ifdef(`NVA3',
|
|||||||
push $r15
|
push $r15
|
||||||
|
|
||||||
// nTy = (h + ((1 << Th) - 1)) >> Th
|
// nTy = (h + ((1 << Th) - 1)) >> Th
|
||||||
ld b32 $r15 D[$r5 + ctx_src_ysize]
|
ld b32 $r15 D[$r5 + #ctx_src_ysize]
|
||||||
mov $r11 1
|
mov $r11 1
|
||||||
shl b32 $r11 $r8
|
shl b32 $r11 $r8
|
||||||
sub b32 $r11 1
|
sub b32 $r11 1
|
||||||
@ -629,7 +631,7 @@ ifdef(`NVA3',
|
|||||||
// Tz = z >> Td
|
// Tz = z >> Td
|
||||||
// Op += Tzo << Tys
|
// Op += Tzo << Tys
|
||||||
// Ts = Tys + Td
|
// Ts = Tys + Td
|
||||||
ld b32 $r8 D[$r5 + ctx_src_zoff]
|
ld b32 $r8 D[$r5 + #ctx_src_zoff]
|
||||||
mov $r14 1
|
mov $r14 1
|
||||||
shl b32 $r14 $r9
|
shl b32 $r14 $r9
|
||||||
sub b32 $r14 1
|
sub b32 $r14 1
|
||||||
@ -656,8 +658,8 @@ ifdef(`NVA3',
|
|||||||
|
|
||||||
// SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
|
// SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
|
||||||
// CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
|
// CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
|
||||||
ld b32 $r7 D[$r5 + ctx_src_address_low]
|
ld b32 $r7 D[$r5 + #ctx_src_address_low]
|
||||||
ld b32 $r8 D[$r5 + ctx_src_address_high]
|
ld b32 $r8 D[$r5 + #ctx_src_address_high]
|
||||||
add b32 $r10 $r12
|
add b32 $r10 $r12
|
||||||
add b32 $r7 $r10
|
add b32 $r7 $r10
|
||||||
adc b32 $r8 0
|
adc b32 $r8 0
|
||||||
@ -677,14 +679,14 @@ cmd_exec_set_surface_linear:
|
|||||||
xbit $r6 $flags $p2
|
xbit $r6 $flags $p2
|
||||||
add b32 $r6 0x202
|
add b32 $r6 0x202
|
||||||
shl b32 $r6 8
|
shl b32 $r6 8
|
||||||
ld b32 $r7 D[$r5 + ctx_src_address_low]
|
ld b32 $r7 D[$r5 + #ctx_src_address_low]
|
||||||
iowr I[$r6 + 0x000] $r7
|
iowr I[$r6 + 0x000] $r7
|
||||||
add b32 $r6 0x400
|
add b32 $r6 0x400
|
||||||
ld b32 $r7 D[$r5 + ctx_src_address_high]
|
ld b32 $r7 D[$r5 + #ctx_src_address_high]
|
||||||
shl b32 $r7 16
|
shl b32 $r7 16
|
||||||
iowr I[$r6 + 0x000] $r7
|
iowr I[$r6 + 0x000] $r7
|
||||||
add b32 $r6 0x400
|
add b32 $r6 0x400
|
||||||
ld b32 $r7 D[$r5 + ctx_src_pitch]
|
ld b32 $r7 D[$r5 + #ctx_src_pitch]
|
||||||
iowr I[$r6 + 0x000] $r7
|
iowr I[$r6 + 0x000] $r7
|
||||||
ret
|
ret
|
||||||
|
|
||||||
@ -697,7 +699,7 @@ cmd_exec_wait:
|
|||||||
loop:
|
loop:
|
||||||
iord $r1 I[$r0]
|
iord $r1 I[$r0]
|
||||||
and $r1 1
|
and $r1 1
|
||||||
bra ne loop
|
bra ne #loop
|
||||||
pop $r1
|
pop $r1
|
||||||
pop $r0
|
pop $r0
|
||||||
ret
|
ret
|
||||||
@ -705,18 +707,18 @@ cmd_exec_wait:
|
|||||||
cmd_exec_query:
|
cmd_exec_query:
|
||||||
// if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
|
// if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
|
||||||
xbit $r4 $r3 13
|
xbit $r4 $r3 13
|
||||||
bra ne query_counter
|
bra ne #query_counter
|
||||||
call cmd_exec_wait
|
call #cmd_exec_wait
|
||||||
mov $r4 0x80c
|
mov $r4 0x80c
|
||||||
shl b32 $r4 6
|
shl b32 $r4 6
|
||||||
ld b32 $r5 D[$r0 + ctx_query_address_low]
|
ld b32 $r5 D[$r0 + #ctx_query_address_low]
|
||||||
add b32 $r5 4
|
add b32 $r5 4
|
||||||
iowr I[$r4 + 0x000] $r5
|
iowr I[$r4 + 0x000] $r5
|
||||||
iowr I[$r4 + 0x100] $r0
|
iowr I[$r4 + 0x100] $r0
|
||||||
mov $r5 0xc
|
mov $r5 0xc
|
||||||
iowr I[$r4 + 0x200] $r5
|
iowr I[$r4 + 0x200] $r5
|
||||||
add b32 $r4 0x400
|
add b32 $r4 0x400
|
||||||
ld b32 $r5 D[$r0 + ctx_query_address_high]
|
ld b32 $r5 D[$r0 + #ctx_query_address_high]
|
||||||
shl b32 $r5 16
|
shl b32 $r5 16
|
||||||
iowr I[$r4 + 0x000] $r5
|
iowr I[$r4 + 0x000] $r5
|
||||||
add b32 $r4 0x500
|
add b32 $r4 0x500
|
||||||
@ -741,16 +743,16 @@ cmd_exec_query:
|
|||||||
|
|
||||||
// write COUNTER
|
// write COUNTER
|
||||||
query_counter:
|
query_counter:
|
||||||
call cmd_exec_wait
|
call #cmd_exec_wait
|
||||||
mov $r4 0x80c
|
mov $r4 0x80c
|
||||||
shl b32 $r4 6
|
shl b32 $r4 6
|
||||||
ld b32 $r5 D[$r0 + ctx_query_address_low]
|
ld b32 $r5 D[$r0 + #ctx_query_address_low]
|
||||||
iowr I[$r4 + 0x000] $r5
|
iowr I[$r4 + 0x000] $r5
|
||||||
iowr I[$r4 + 0x100] $r0
|
iowr I[$r4 + 0x100] $r0
|
||||||
mov $r5 0x4
|
mov $r5 0x4
|
||||||
iowr I[$r4 + 0x200] $r5
|
iowr I[$r4 + 0x200] $r5
|
||||||
add b32 $r4 0x400
|
add b32 $r4 0x400
|
||||||
ld b32 $r5 D[$r0 + ctx_query_address_high]
|
ld b32 $r5 D[$r0 + #ctx_query_address_high]
|
||||||
shl b32 $r5 16
|
shl b32 $r5 16
|
||||||
iowr I[$r4 + 0x000] $r5
|
iowr I[$r4 + 0x000] $r5
|
||||||
add b32 $r4 0x500
|
add b32 $r4 0x500
|
||||||
@ -759,7 +761,7 @@ cmd_exec_query:
|
|||||||
mov $r5 0x00001110
|
mov $r5 0x00001110
|
||||||
sethi $r5 0x13120000
|
sethi $r5 0x13120000
|
||||||
iowr I[$r4 + 0x100] $r5
|
iowr I[$r4 + 0x100] $r5
|
||||||
ld b32 $r5 D[$r0 + ctx_query_counter]
|
ld b32 $r5 D[$r0 + #ctx_query_counter]
|
||||||
add b32 $r4 0x500
|
add b32 $r4 0x500
|
||||||
iowr I[$r4 + 0x000] $r5
|
iowr I[$r4 + 0x000] $r5
|
||||||
mov $r5 0x00002601
|
mov $r5 0x00002601
|
||||||
@ -787,22 +789,22 @@ cmd_exec_query:
|
|||||||
// $r2: hostirq state
|
// $r2: hostirq state
|
||||||
// $r3: data
|
// $r3: data
|
||||||
cmd_exec:
|
cmd_exec:
|
||||||
call cmd_exec_wait
|
call #cmd_exec_wait
|
||||||
|
|
||||||
// if format requested, call function to calculate it, otherwise
|
// if format requested, call function to calculate it, otherwise
|
||||||
// fill in cpp/xcnt for both surfaces as if (cpp == 1)
|
// fill in cpp/xcnt for both surfaces as if (cpp == 1)
|
||||||
xbit $r15 $r3 0
|
xbit $r15 $r3 0
|
||||||
bra e cmd_exec_no_format
|
bra e #cmd_exec_no_format
|
||||||
call cmd_exec_set_format
|
call #cmd_exec_set_format
|
||||||
mov $r4 0x200
|
mov $r4 0x200
|
||||||
bra cmd_exec_init_src_surface
|
bra #cmd_exec_init_src_surface
|
||||||
cmd_exec_no_format:
|
cmd_exec_no_format:
|
||||||
mov $r6 0x810
|
mov $r6 0x810
|
||||||
shl b32 $r6 6
|
shl b32 $r6 6
|
||||||
mov $r7 1
|
mov $r7 1
|
||||||
st b32 D[$r0 + ctx_src_cpp] $r7
|
st b32 D[$r0 + #ctx_src_cpp] $r7
|
||||||
st b32 D[$r0 + ctx_dst_cpp] $r7
|
st b32 D[$r0 + #ctx_dst_cpp] $r7
|
||||||
ld b32 $r7 D[$r0 + ctx_xcnt]
|
ld b32 $r7 D[$r0 + #ctx_xcnt]
|
||||||
iowr I[$r6 + 0x000] $r7
|
iowr I[$r6 + 0x000] $r7
|
||||||
iowr I[$r6 + 0x100] $r7
|
iowr I[$r6 + 0x100] $r7
|
||||||
clear b32 $r4
|
clear b32 $r4
|
||||||
@ -811,28 +813,28 @@ cmd_exec:
|
|||||||
bclr $flags $p2
|
bclr $flags $p2
|
||||||
clear b32 $r5
|
clear b32 $r5
|
||||||
xbit $r15 $r3 4
|
xbit $r15 $r3 4
|
||||||
bra e src_tiled
|
bra e #src_tiled
|
||||||
call cmd_exec_set_surface_linear
|
call #cmd_exec_set_surface_linear
|
||||||
bra cmd_exec_init_dst_surface
|
bra #cmd_exec_init_dst_surface
|
||||||
src_tiled:
|
src_tiled:
|
||||||
call cmd_exec_set_surface_tiled
|
call #cmd_exec_set_surface_tiled
|
||||||
bset $r4 7
|
bset $r4 7
|
||||||
|
|
||||||
cmd_exec_init_dst_surface:
|
cmd_exec_init_dst_surface:
|
||||||
bset $flags $p2
|
bset $flags $p2
|
||||||
mov $r5 ctx_dst_address_high - ctx_src_address_high
|
mov $r5 #ctx_dst_address_high - #ctx_src_address_high
|
||||||
xbit $r15 $r3 8
|
xbit $r15 $r3 8
|
||||||
bra e dst_tiled
|
bra e #dst_tiled
|
||||||
call cmd_exec_set_surface_linear
|
call #cmd_exec_set_surface_linear
|
||||||
bra cmd_exec_kick
|
bra #cmd_exec_kick
|
||||||
dst_tiled:
|
dst_tiled:
|
||||||
call cmd_exec_set_surface_tiled
|
call #cmd_exec_set_surface_tiled
|
||||||
bset $r4 8
|
bset $r4 8
|
||||||
|
|
||||||
cmd_exec_kick:
|
cmd_exec_kick:
|
||||||
mov $r5 0x800
|
mov $r5 0x800
|
||||||
shl b32 $r5 6
|
shl b32 $r5 6
|
||||||
ld b32 $r6 D[$r0 + ctx_ycnt]
|
ld b32 $r6 D[$r0 + #ctx_ycnt]
|
||||||
iowr I[$r5 + 0x100] $r6
|
iowr I[$r5 + 0x100] $r6
|
||||||
mov $r6 0x0041
|
mov $r6 0x0041
|
||||||
// SRC_TARGET = 1, DST_TARGET = 2
|
// SRC_TARGET = 1, DST_TARGET = 2
|
||||||
@ -842,8 +844,8 @@ cmd_exec:
|
|||||||
|
|
||||||
// if requested, queue up a QUERY write after the copy has completed
|
// if requested, queue up a QUERY write after the copy has completed
|
||||||
xbit $r15 $r3 12
|
xbit $r15 $r3 12
|
||||||
bra e cmd_exec_done
|
bra e #cmd_exec_done
|
||||||
call cmd_exec_query
|
call #cmd_exec_query
|
||||||
|
|
||||||
cmd_exec_done:
|
cmd_exec_done:
|
||||||
ret
|
ret
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user