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riscv: dts: add initial Sophgo SG2042 SoC device tree
Milk-V Pioneer motherboard is powered by SG2042. SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores - 4 cores per cluster, 16 clusters on chip - More info is available at [1]. Currently only support booting into console with only uart, other features will be added soon later. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Chao Wei <chao.wei@sophgo.com> Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Co-developed-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Chen Wang
Conor Dooley
parent
942e02e150
commit
967a94a92a
@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
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M: Chao Wei <chao.wei@sophgo.com>
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M: Chen Wang <unicorn_wang@outlook.com>
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S: Maintained
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F: arch/riscv/boot/dts/sophgo/
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F: Documentation/devicetree/bindings/riscv/sophgo.yaml
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SOUND
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2000
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
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2000
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
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File diff suppressed because it is too large
Load Diff
325
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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325
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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@ -0,0 +1,325 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "sg2042-cpus.dtsi"
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/ {
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compatible = "sophgo,sg2042";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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aliases {
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serial0 = &uart0;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clint_mswi: interrupt-controller@7094000000 {
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compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
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reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
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interrupts-extended = <&cpu0_intc 3>,
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<&cpu1_intc 3>,
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<&cpu2_intc 3>,
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<&cpu3_intc 3>,
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<&cpu4_intc 3>,
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<&cpu5_intc 3>,
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<&cpu6_intc 3>,
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<&cpu7_intc 3>,
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<&cpu8_intc 3>,
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<&cpu9_intc 3>,
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<&cpu10_intc 3>,
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<&cpu11_intc 3>,
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<&cpu12_intc 3>,
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<&cpu13_intc 3>,
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<&cpu14_intc 3>,
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<&cpu15_intc 3>,
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<&cpu16_intc 3>,
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<&cpu17_intc 3>,
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<&cpu18_intc 3>,
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<&cpu19_intc 3>,
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<&cpu20_intc 3>,
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<&cpu21_intc 3>,
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<&cpu22_intc 3>,
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<&cpu23_intc 3>,
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<&cpu24_intc 3>,
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<&cpu25_intc 3>,
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<&cpu26_intc 3>,
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<&cpu27_intc 3>,
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<&cpu28_intc 3>,
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<&cpu29_intc 3>,
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<&cpu30_intc 3>,
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<&cpu31_intc 3>,
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<&cpu32_intc 3>,
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<&cpu33_intc 3>,
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<&cpu34_intc 3>,
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<&cpu35_intc 3>,
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<&cpu36_intc 3>,
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<&cpu37_intc 3>,
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<&cpu38_intc 3>,
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<&cpu39_intc 3>,
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<&cpu40_intc 3>,
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<&cpu41_intc 3>,
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<&cpu42_intc 3>,
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<&cpu43_intc 3>,
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<&cpu44_intc 3>,
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<&cpu45_intc 3>,
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<&cpu46_intc 3>,
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<&cpu47_intc 3>,
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<&cpu48_intc 3>,
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<&cpu49_intc 3>,
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<&cpu50_intc 3>,
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<&cpu51_intc 3>,
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<&cpu52_intc 3>,
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<&cpu53_intc 3>,
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<&cpu54_intc 3>,
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<&cpu55_intc 3>,
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<&cpu56_intc 3>,
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<&cpu57_intc 3>,
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<&cpu58_intc 3>,
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<&cpu59_intc 3>,
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<&cpu60_intc 3>,
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<&cpu61_intc 3>,
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<&cpu62_intc 3>,
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<&cpu63_intc 3>;
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};
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clint_mtimer0: timer@70ac000000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu0_intc 7>,
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<&cpu1_intc 7>,
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<&cpu2_intc 7>,
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<&cpu3_intc 7>;
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};
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clint_mtimer1: timer@70ac010000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu4_intc 7>,
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<&cpu5_intc 7>,
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<&cpu6_intc 7>,
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<&cpu7_intc 7>;
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};
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clint_mtimer2: timer@70ac020000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu8_intc 7>,
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<&cpu9_intc 7>,
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<&cpu10_intc 7>,
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<&cpu11_intc 7>;
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};
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clint_mtimer3: timer@70ac030000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu12_intc 7>,
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<&cpu13_intc 7>,
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<&cpu14_intc 7>,
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<&cpu15_intc 7>;
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};
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clint_mtimer4: timer@70ac040000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu16_intc 7>,
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<&cpu17_intc 7>,
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<&cpu18_intc 7>,
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<&cpu19_intc 7>;
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};
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clint_mtimer5: timer@70ac050000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu20_intc 7>,
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<&cpu21_intc 7>,
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<&cpu22_intc 7>,
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<&cpu23_intc 7>;
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};
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clint_mtimer6: timer@70ac060000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu24_intc 7>,
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<&cpu25_intc 7>,
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<&cpu26_intc 7>,
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<&cpu27_intc 7>;
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};
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clint_mtimer7: timer@70ac070000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu28_intc 7>,
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<&cpu29_intc 7>,
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<&cpu30_intc 7>,
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<&cpu31_intc 7>;
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};
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clint_mtimer8: timer@70ac080000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu32_intc 7>,
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<&cpu33_intc 7>,
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<&cpu34_intc 7>,
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<&cpu35_intc 7>;
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};
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clint_mtimer9: timer@70ac090000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu36_intc 7>,
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<&cpu37_intc 7>,
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<&cpu38_intc 7>,
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<&cpu39_intc 7>;
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};
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clint_mtimer10: timer@70ac0a0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu40_intc 7>,
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<&cpu41_intc 7>,
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<&cpu42_intc 7>,
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<&cpu43_intc 7>;
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};
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clint_mtimer11: timer@70ac0b0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu44_intc 7>,
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<&cpu45_intc 7>,
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<&cpu46_intc 7>,
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<&cpu47_intc 7>;
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};
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clint_mtimer12: timer@70ac0c0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu48_intc 7>,
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<&cpu49_intc 7>,
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<&cpu50_intc 7>,
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<&cpu51_intc 7>;
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};
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clint_mtimer13: timer@70ac0d0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu52_intc 7>,
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<&cpu53_intc 7>,
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<&cpu54_intc 7>,
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<&cpu55_intc 7>;
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};
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clint_mtimer14: timer@70ac0e0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu56_intc 7>,
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<&cpu57_intc 7>,
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<&cpu58_intc 7>,
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<&cpu59_intc 7>;
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};
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clint_mtimer15: timer@70ac0f0000 {
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compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
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reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
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interrupts-extended = <&cpu60_intc 7>,
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<&cpu61_intc 7>,
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<&cpu62_intc 7>,
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<&cpu63_intc 7>;
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};
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intc: interrupt-controller@7090000000 {
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compatible = "sophgo,sg2042-plic", "thead,c900-plic";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
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interrupt-controller;
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interrupts-extended =
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<&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>,
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<&cpu4_intc 11>, <&cpu4_intc 9>,
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<&cpu5_intc 11>, <&cpu5_intc 9>,
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<&cpu6_intc 11>, <&cpu6_intc 9>,
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<&cpu7_intc 11>, <&cpu7_intc 9>,
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<&cpu8_intc 11>, <&cpu8_intc 9>,
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<&cpu9_intc 11>, <&cpu9_intc 9>,
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<&cpu10_intc 11>, <&cpu10_intc 9>,
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<&cpu11_intc 11>, <&cpu11_intc 9>,
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<&cpu12_intc 11>, <&cpu12_intc 9>,
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<&cpu13_intc 11>, <&cpu13_intc 9>,
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<&cpu14_intc 11>, <&cpu14_intc 9>,
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<&cpu15_intc 11>, <&cpu15_intc 9>,
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<&cpu16_intc 11>, <&cpu16_intc 9>,
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<&cpu17_intc 11>, <&cpu17_intc 9>,
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<&cpu18_intc 11>, <&cpu18_intc 9>,
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<&cpu19_intc 11>, <&cpu19_intc 9>,
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<&cpu20_intc 11>, <&cpu20_intc 9>,
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<&cpu21_intc 11>, <&cpu21_intc 9>,
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<&cpu22_intc 11>, <&cpu22_intc 9>,
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<&cpu23_intc 11>, <&cpu23_intc 9>,
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<&cpu24_intc 11>, <&cpu24_intc 9>,
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<&cpu25_intc 11>, <&cpu25_intc 9>,
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<&cpu26_intc 11>, <&cpu26_intc 9>,
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<&cpu27_intc 11>, <&cpu27_intc 9>,
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<&cpu28_intc 11>, <&cpu28_intc 9>,
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<&cpu29_intc 11>, <&cpu29_intc 9>,
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<&cpu30_intc 11>, <&cpu30_intc 9>,
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<&cpu31_intc 11>, <&cpu31_intc 9>,
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<&cpu32_intc 11>, <&cpu32_intc 9>,
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<&cpu33_intc 11>, <&cpu33_intc 9>,
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<&cpu34_intc 11>, <&cpu34_intc 9>,
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<&cpu35_intc 11>, <&cpu35_intc 9>,
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<&cpu36_intc 11>, <&cpu36_intc 9>,
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<&cpu37_intc 11>, <&cpu37_intc 9>,
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<&cpu38_intc 11>, <&cpu38_intc 9>,
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<&cpu39_intc 11>, <&cpu39_intc 9>,
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<&cpu40_intc 11>, <&cpu40_intc 9>,
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<&cpu41_intc 11>, <&cpu41_intc 9>,
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<&cpu42_intc 11>, <&cpu42_intc 9>,
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<&cpu43_intc 11>, <&cpu43_intc 9>,
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<&cpu44_intc 11>, <&cpu44_intc 9>,
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<&cpu45_intc 11>, <&cpu45_intc 9>,
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<&cpu46_intc 11>, <&cpu46_intc 9>,
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<&cpu47_intc 11>, <&cpu47_intc 9>,
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<&cpu48_intc 11>, <&cpu48_intc 9>,
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<&cpu49_intc 11>, <&cpu49_intc 9>,
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<&cpu50_intc 11>, <&cpu50_intc 9>,
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<&cpu51_intc 11>, <&cpu51_intc 9>,
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<&cpu52_intc 11>, <&cpu52_intc 9>,
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<&cpu53_intc 11>, <&cpu53_intc 9>,
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<&cpu54_intc 11>, <&cpu54_intc 9>,
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<&cpu55_intc 11>, <&cpu55_intc 9>,
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<&cpu56_intc 11>, <&cpu56_intc 9>,
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<&cpu57_intc 11>, <&cpu57_intc 9>,
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<&cpu58_intc 11>, <&cpu58_intc 9>,
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<&cpu59_intc 11>, <&cpu59_intc 9>,
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<&cpu60_intc 11>, <&cpu60_intc 9>,
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<&cpu61_intc 11>, <&cpu61_intc 9>,
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<&cpu62_intc 11>, <&cpu62_intc 9>,
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<&cpu63_intc 11>, <&cpu63_intc 9>;
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riscv,ndev = <224>;
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};
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uart0: serial@7040000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
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interrupt-parent = <&intc>;
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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};
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};
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