mirror of
https://github.com/torvalds/linux.git
synced 2024-12-26 12:52:30 +00:00
Merge branch 'parisc-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc updates from Helge Deller: "The majority of the patches are reverts of previous commits regarding the parisc-specific low level spinlocking code and barrier handling, with which we tried to fix CPU stalls on our build servers. In the end John David Anglin found the culprit: We missed a define for atomic64_set_release(). This seems to have fixed our issues, so now it's good to remove the unnecessary code again. Other than that it's trivial stuff: Spelling fixes, constifications and such" * 'parisc-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: make the log level string for register dumps const parisc: Do not use an ordered store in pa_tlb_lock() Revert "parisc: Revert "Release spinlocks using ordered store"" Revert "parisc: Use ldcw instruction for SMP spinlock release barrier" Revert "parisc: Drop LDCW barrier in CAS code when running UP" Revert "parisc: Improve interrupt handling in arch_spin_lock_flags()" parisc: Replace HTTP links with HTTPS ones parisc: elf.h: delete a duplicated word parisc: Report bad pages as HardwareCorrupted parisc: Convert to BIT_MASK() and BIT_WORD()
This commit is contained in:
Linus Torvalds
commit
95ffa67658
@ -285,7 +285,7 @@ config SMP
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On a uniprocessor machine, the kernel will run faster if you say N.
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See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
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available at <http://www.tldp.org/docs.html#howto>.
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available at <https://www.tldp.org/docs.html#howto>.
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If you don't know what to do here, say N.
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@ -12,21 +12,6 @@
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#include <asm/barrier.h>
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#include <linux/atomic.h>
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/*
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* HP-PARISC specific bit operations
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* for a detailed description of the functions please refer
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* to include/asm-i386/bitops.h or kerneldoc
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*/
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#if __BITS_PER_LONG == 64
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#define SHIFT_PER_LONG 6
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#else
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#define SHIFT_PER_LONG 5
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#endif
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#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
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/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
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* on use of volatile and __*_bit() (set/clear/change):
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* *_bit() want use of volatile.
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@ -35,10 +20,10 @@
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static __inline__ void set_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr |= mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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@ -46,21 +31,21 @@ static __inline__ void set_bit(int nr, volatile unsigned long * addr)
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static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr &= mask;
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*addr &= ~mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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}
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static __inline__ void change_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr ^= mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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@ -68,12 +53,12 @@ static __inline__ void change_bit(int nr, volatile unsigned long * addr)
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static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
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unsigned long mask = BIT_MASK(nr);
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unsigned long old;
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unsigned long flags;
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int set;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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old = *addr;
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set = (old & mask) ? 1 : 0;
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@ -86,12 +71,12 @@ static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
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static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
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unsigned long mask = BIT_MASK(nr);
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unsigned long old;
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unsigned long flags;
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int set;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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old = *addr;
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set = (old & mask) ? 1 : 0;
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@ -104,11 +89,11 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
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static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
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unsigned long mask = BIT_MASK(nr);
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unsigned long oldbit;
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unsigned long flags;
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addr += (nr >> SHIFT_PER_LONG);
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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oldbit = *addr;
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*addr = oldbit ^ mask;
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@ -152,7 +152,7 @@
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/* The following are PA function descriptors
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*
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* addr: the absolute address of the function
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* gp: either the data pointer (r27) for non-PIC code or the
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* gp: either the data pointer (r27) for non-PIC code or
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* the PLT pointer (r19) for PIC code */
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/* Format for the Elf32 Function descriptor */
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@ -10,34 +10,25 @@
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static inline int arch_spin_is_locked(arch_spinlock_t *x)
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{
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volatile unsigned int *a = __ldcw_align(x);
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smp_mb();
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return *a == 0;
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}
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static inline void arch_spin_lock(arch_spinlock_t *x)
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#define arch_spin_lock(lock) arch_spin_lock_flags(lock, 0)
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static inline void arch_spin_lock_flags(arch_spinlock_t *x,
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unsigned long flags)
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{
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volatile unsigned int *a;
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a = __ldcw_align(x);
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while (__ldcw(a) == 0)
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while (*a == 0)
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cpu_relax();
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}
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static inline void arch_spin_lock_flags(arch_spinlock_t *x,
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unsigned long flags)
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{
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volatile unsigned int *a;
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unsigned long flags_dis;
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a = __ldcw_align(x);
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while (__ldcw(a) == 0) {
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local_save_flags(flags_dis);
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local_irq_restore(flags);
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while (*a == 0)
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cpu_relax();
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local_irq_restore(flags_dis);
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}
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if (flags & PSW_SM_I) {
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local_irq_enable();
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cpu_relax();
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local_irq_disable();
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} else
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cpu_relax();
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}
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#define arch_spin_lock_flags arch_spin_lock_flags
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@ -46,12 +37,8 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
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volatile unsigned int *a;
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a = __ldcw_align(x);
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#ifdef CONFIG_SMP
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(void) __ldcw(a);
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#else
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mb();
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#endif
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*a = 1;
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/* Release with ordered store. */
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__asm__ __volatile__("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *x)
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@ -454,7 +454,6 @@
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nop
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LDREG 0(\ptp),\pte
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bb,<,n \pte,_PAGE_PRESENT_BIT,3f
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LDCW 0(\tmp),\tmp1
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b \fault
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stw \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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@ -464,23 +463,26 @@
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3:
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.endm
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/* Release pa_tlb_lock lock without reloading lock address. */
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.macro tlb_unlock0 spc,tmp,tmp1
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/* Release pa_tlb_lock lock without reloading lock address.
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Note that the values in the register spc are limited to
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NR_SPACE_IDS (262144). Thus, the stw instruction always
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stores a nonzero value even when register spc is 64 bits.
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We use an ordered store to ensure all prior accesses are
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performed prior to releasing the lock. */
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.macro tlb_unlock0 spc,tmp
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#ifdef CONFIG_SMP
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98: or,COND(=) %r0,\spc,%r0
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LDCW 0(\tmp),\tmp1
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or,COND(=) %r0,\spc,%r0
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stw \spc,0(\tmp)
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stw,ma \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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#endif
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.endm
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/* Release pa_tlb_lock lock. */
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.macro tlb_unlock1 spc,tmp,tmp1
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.macro tlb_unlock1 spc,tmp
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#ifdef CONFIG_SMP
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98: load_pa_tlb_lock \tmp
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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tlb_unlock0 \spc,\tmp,\tmp1
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tlb_unlock0 \spc,\tmp
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#endif
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.endm
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@ -1163,7 +1165,7 @@ dtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1189,7 +1191,7 @@ nadtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1223,7 +1225,7 @@ dtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1256,7 +1258,7 @@ nadtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1285,7 +1287,7 @@ dtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1313,7 +1315,7 @@ nadtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1420,7 +1422,7 @@ itlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1444,7 +1446,7 @@ naitlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1478,7 +1480,7 @@ itlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1502,7 +1504,7 @@ naitlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1532,7 +1534,7 @@ itlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1552,7 +1554,7 @@ naitlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1582,7 +1584,7 @@ dbit_trap_20w:
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idtlbt pte,prot
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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#else
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@ -1608,7 +1610,7 @@ dbit_trap_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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@ -1628,7 +1630,7 @@ dbit_trap_20:
|
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idtlbt pte,prot
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|
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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#endif
|
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|
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@ -18,6 +18,8 @@
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/pgtable.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/swapops.h>
|
||||
|
||||
#include <asm/pdc.h>
|
||||
#include <asm/pdcpat.h>
|
||||
@ -230,6 +232,7 @@ void __init pdc_pdt_init(void)
|
||||
|
||||
/* mark memory page bad */
|
||||
memblock_reserve(pdt_entry[i] & PAGE_MASK, PAGE_SIZE);
|
||||
num_poisoned_pages_inc();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -640,11 +640,7 @@ cas_action:
|
||||
sub,<> %r28, %r25, %r0
|
||||
2: stw %r24, 0(%r26)
|
||||
/* Free lock */
|
||||
#ifdef CONFIG_SMP
|
||||
98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
|
||||
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
|
||||
#endif
|
||||
stw %r20, 0(%sr2,%r20)
|
||||
stw,ma %r20, 0(%sr2,%r20)
|
||||
#if ENABLE_LWS_DEBUG
|
||||
/* Clear thread register indicator */
|
||||
stw %r0, 4(%sr2,%r20)
|
||||
@ -658,11 +654,7 @@ cas_action:
|
||||
3:
|
||||
/* Error occurred on load or store */
|
||||
/* Free lock */
|
||||
#ifdef CONFIG_SMP
|
||||
98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
|
||||
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
|
||||
#endif
|
||||
stw %r20, 0(%sr2,%r20)
|
||||
stw,ma %r20, 0(%sr2,%r20)
|
||||
#if ENABLE_LWS_DEBUG
|
||||
stw %r0, 4(%sr2,%r20)
|
||||
#endif
|
||||
@ -863,11 +855,7 @@ cas2_action:
|
||||
|
||||
cas2_end:
|
||||
/* Free lock */
|
||||
#ifdef CONFIG_SMP
|
||||
98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
|
||||
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
|
||||
#endif
|
||||
stw %r20, 0(%sr2,%r20)
|
||||
stw,ma %r20, 0(%sr2,%r20)
|
||||
/* Enable interrupts */
|
||||
ssm PSW_SM_I, %r0
|
||||
/* Return to userspace, set no error */
|
||||
@ -877,11 +865,7 @@ cas2_end:
|
||||
22:
|
||||
/* Error occurred on load or store */
|
||||
/* Free lock */
|
||||
#ifdef CONFIG_SMP
|
||||
98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
|
||||
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
|
||||
#endif
|
||||
stw %r20, 0(%sr2,%r20)
|
||||
stw,ma %r20, 0(%sr2,%r20)
|
||||
ssm PSW_SM_I, %r0
|
||||
ldo 1(%r0),%r28
|
||||
b lws_exit
|
||||
|
||||
@ -75,7 +75,7 @@ static int printbinary(char *buf, unsigned long x, int nbits)
|
||||
lvl, f, (x), (x+3), (r)[(x)+0], (r)[(x)+1], \
|
||||
(r)[(x)+2], (r)[(x)+3])
|
||||
|
||||
static void print_gr(char *level, struct pt_regs *regs)
|
||||
static void print_gr(const char *level, struct pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
char buf[64];
|
||||
@ -89,7 +89,7 @@ static void print_gr(char *level, struct pt_regs *regs)
|
||||
PRINTREGS(level, regs->gr, "r", RFMT, i);
|
||||
}
|
||||
|
||||
static void print_fr(char *level, struct pt_regs *regs)
|
||||
static void print_fr(const char *level, struct pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
char buf[64];
|
||||
@ -119,7 +119,7 @@ static void print_fr(char *level, struct pt_regs *regs)
|
||||
void show_regs(struct pt_regs *regs)
|
||||
{
|
||||
int i, user;
|
||||
char *level;
|
||||
const char *level;
|
||||
unsigned long cr30, cr31;
|
||||
|
||||
user = user_mode(regs);
|
||||
|
||||
@ -750,7 +750,7 @@ unsigned long alloc_sid(void)
|
||||
free_space_ids--;
|
||||
|
||||
index = find_next_zero_bit(space_id, NR_SPACE_IDS, space_id_index);
|
||||
space_id[index >> SHIFT_PER_LONG] |= (1L << (index & (BITS_PER_LONG - 1)));
|
||||
space_id[BIT_WORD(index)] |= BIT_MASK(index);
|
||||
space_id_index = index;
|
||||
|
||||
spin_unlock(&sid_lock);
|
||||
@ -761,16 +761,16 @@ unsigned long alloc_sid(void)
|
||||
void free_sid(unsigned long spaceid)
|
||||
{
|
||||
unsigned long index = spaceid >> SPACEID_SHIFT;
|
||||
unsigned long *dirty_space_offset;
|
||||
unsigned long *dirty_space_offset, mask;
|
||||
|
||||
dirty_space_offset = dirty_space_id + (index >> SHIFT_PER_LONG);
|
||||
index &= (BITS_PER_LONG - 1);
|
||||
dirty_space_offset = &dirty_space_id[BIT_WORD(index)];
|
||||
mask = BIT_MASK(index);
|
||||
|
||||
spin_lock(&sid_lock);
|
||||
|
||||
BUG_ON(*dirty_space_offset & (1L << index)); /* attempt to free space id twice */
|
||||
BUG_ON(*dirty_space_offset & mask); /* attempt to free space id twice */
|
||||
|
||||
*dirty_space_offset |= (1L << index);
|
||||
*dirty_space_offset |= mask;
|
||||
dirty_space_ids++;
|
||||
|
||||
spin_unlock(&sid_lock);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user