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media: cx23885: Ryzen DMA related RiSC engine stall fixes
This bug affects all of Hauppauge QuadHD boards when used on all Ryzen platforms and some XEON platforms. On these platforms it is possible to error out the RiSC engine and cause it to stall, whereafter the only way to reset the board to a working state is to reboot. This is the fatal condition with current driver: [ 255.663598] cx23885: cx23885[0]: mpeg risc op code error [ 255.663607] cx23885: cx23885[0]: TS1 B - dma channel status dump [ 255.663612] cx23885: cx23885[0]: cmds: init risc lo : 0xffe54000 [ 255.663615] cx23885: cx23885[0]: cmds: init risc hi : 0x00000000 [ 255.663619] cx23885: cx23885[0]: cmds: cdt base : 0x00010870 [ 255.663622] cx23885: cx23885[0]: cmds: cdt size : 0x0000000a [ 255.663625] cx23885: cx23885[0]: cmds: iq base : 0x00010630 [ 255.663629] cx23885: cx23885[0]: cmds: iq size : 0x00000010 [ 255.663632] cx23885: cx23885[0]: cmds: risc pc lo : 0xffe54018 [ 255.663636] cx23885: cx23885[0]: cmds: risc pc hi : 0x00000000 [ 255.663639] cx23885: cx23885[0]: cmds: iq wr ptr : 0x00004192 [ 255.663642] cx23885: cx23885[0]: cmds: iq rd ptr : 0x0000418c [ 255.663645] cx23885: cx23885[0]: cmds: cdt current : 0x00010898 [ 255.663649] cx23885: cx23885[0]: cmds: pci target lo : 0xf85ca340 [ 255.663652] cx23885: cx23885[0]: cmds: pci target hi : 0x00000000 [ 255.663655] cx23885: cx23885[0]: cmds: line / byte : 0x000c0000 [ 255.663659] cx23885: cx23885[0]: risc0: [ 255.663661] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663666] cx23885: cx23885[0]: risc1: [ 255.663667] 0xf85ca050 [ INVALID sol 22 20 19 18 resync 13 count=80 ] [ 255.663674] cx23885: cx23885[0]: risc2: [ 255.663674] 0x00000000 [ INVALID count=0 ] [ 255.663678] cx23885: cx23885[0]: risc3: [ 255.663679] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663684] cx23885: cx23885[0]: (0x00010630) iq 0: [ 255.663685] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663690] cx23885: cx23885[0]: iq 1: 0xf85ca630 [ arg #1 ] [ 255.663693] cx23885: cx23885[0]: iq 2: 0x00000000 [ arg #2 ] [ 255.663696] cx23885: cx23885[0]: (0x0001063c) iq 3: [ 255.663697] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663702] cx23885: cx23885[0]: iq 4: 0xf85ca920 [ arg #1 ] [ 255.663705] cx23885: cx23885[0]: iq 5: 0x00000000 [ arg #2 ] [ 255.663709] cx23885: cx23885[0]: (0x00010648) iq 6: [ 255.663709] 0xf85ca340 [ INVALID sol 22 20 19 18 resync 13 count=832 ] [ 255.663716] cx23885: cx23885[0]: (0x0001064c) iq 7: [ 255.663717] 0x00000000 [ INVALID count=0 ] [ 255.663721] cx23885: cx23885[0]: (0x00010650) iq 8: [ 255.663721] 0x00000000 [ INVALID count=0 ] [ 255.663725] cx23885: cx23885[0]: (0x00010654) iq 9: [ 255.663726] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663731] cx23885: cx23885[0]: iq a: 0xf85c9780 [ arg #1 ] [ 255.663734] cx23885: cx23885[0]: iq b: 0x00000000 [ arg #2 ] [ 255.663737] cx23885: cx23885[0]: (0x00010660) iq c: [ 255.663738] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663743] cx23885: cx23885[0]: iq d: 0xf85c9a70 [ arg #1 ] [ 255.663746] cx23885: cx23885[0]: iq e: 0x00000000 [ arg #2 ] [ 255.663749] cx23885: cx23885[0]: (0x0001066c) iq f: [ 255.663750] 0x1c0002f0 [ write sol eol count=752 ] [ 255.663755] cx23885: cx23885[0]: iq 10: 0xf4fa2920 [ arg #1 ] [ 255.663758] cx23885: cx23885[0]: iq 11: 0x00000000 [ arg #2 ] [ 255.663759] cx23885: cx23885[0]: fifo: 0x00005000 -> 0x6000 [ 255.663760] cx23885: cx23885[0]: ctrl: 0x00010630 -> 0x10690 [ 255.663764] cx23885: cx23885[0]: ptr1_reg: 0x00005980 [ 255.663767] cx23885: cx23885[0]: ptr2_reg: 0x000108a8 [ 255.663770] cx23885: cx23885[0]: cnt1_reg: 0x0000000b [ 255.663773] cx23885: cx23885[0]: cnt2_reg: 0x00000003 Included is checks of the TC_REQ and TC_REQ_SET registers during states of board initialization, reset, DMA start, and DMA stop. If both registers are set, this indicates a stall in the RiSC engine, at which point the bridge error is cleared. A small delay is introduced in stop_dma as well, to allow transfers in progress to finish. After application all models work on Ryzen, occasionally yielding: cx23885_clear_bridge_error: dma in progress detected 0x00000001 0x00000001, clearing Signed-off-by: Brad Love <brad@nextdimension.cc> Signed-off-by: Hans Verkuil <hansverk@cisco.com> [hansverk@cisco.com: fix compiler warning of unused 'reg' variable] Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Brad Love
Mauro Carvalho Chehab
parent
3b8315f37d
commit
95f408bbc4
@ -601,6 +601,25 @@ static void cx23885_risc_disasm(struct cx23885_tsport *port,
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}
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}
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static void cx23885_clear_bridge_error(struct cx23885_dev *dev)
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{
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uint32_t reg1_val = cx_read(TC_REQ); /* read-only */
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uint32_t reg2_val = cx_read(TC_REQ_SET);
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if (reg1_val && reg2_val) {
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cx_write(TC_REQ, reg1_val);
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cx_write(TC_REQ_SET, reg2_val);
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cx_read(VID_B_DMA);
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cx_read(VBI_B_DMA);
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cx_read(VID_C_DMA);
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cx_read(VBI_C_DMA);
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dev_info(&dev->pci->dev,
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"dma in progress detected 0x%08x 0x%08x, clearing\n",
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reg1_val, reg2_val);
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}
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}
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static void cx23885_shutdown(struct cx23885_dev *dev)
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{
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/* disable RISC controller */
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@ -646,6 +665,8 @@ static void cx23885_reset(struct cx23885_dev *dev)
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cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
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cx_write(PAD_CTRL, 0x00500300);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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mdelay(100);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
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@ -662,6 +683,11 @@ static void cx23885_reset(struct cx23885_dev *dev)
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cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
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cx23885_gpio_setup(dev);
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cx23885_irq_get_mask(dev);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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}
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@ -676,6 +702,8 @@ static int cx23885_pci_quirks(struct cx23885_dev *dev)
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if (dev->bridge == CX23885_BRIDGE_885)
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cx_clear(RDR_TLCTL0, 1 << 4);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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return 0;
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}
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@ -1352,6 +1380,9 @@ int cx23885_start_dma(struct cx23885_tsport *port,
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dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
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dev->width, dev->height, dev->field);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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/* Stop the fifo and risc engine for this port */
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cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
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@ -1432,16 +1463,26 @@ int cx23885_start_dma(struct cx23885_tsport *port,
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case CX23885_BRIDGE_888:
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/* enable irqs */
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dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
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cx_set(port->reg_dma_ctl, port->dma_ctl_val);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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cx23885_irq_add(dev, port->pci_irqmask);
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cx23885_irq_enable_all(dev);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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break;
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default:
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BUG();
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}
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cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
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cx23885_av_clk(dev, 1);
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@ -1449,6 +1490,11 @@ int cx23885_start_dma(struct cx23885_tsport *port,
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if (debug > 4)
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cx23885_tsport_reg_dump(port);
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cx23885_irq_get_mask(dev);
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/* clear dma in progress */
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cx23885_clear_bridge_error(dev);
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return 0;
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}
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@ -1456,15 +1502,28 @@ static int cx23885_stop_dma(struct cx23885_tsport *port)
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{
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struct cx23885_dev *dev = port->dev;
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u32 reg;
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int delay = 0;
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uint32_t reg1_val;
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uint32_t reg2_val;
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dprintk(1, "%s()\n", __func__);
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/* Stop interrupts and DMA */
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cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
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cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
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/* just in case wait for any dma to complete before allowing dealloc */
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mdelay(20);
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for (delay = 0; delay < 100; delay++) {
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reg1_val = cx_read(TC_REQ);
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reg2_val = cx_read(TC_REQ_SET);
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if (reg1_val == 0 || reg2_val == 0)
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break;
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mdelay(1);
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}
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dev_dbg(&dev->pci->dev, "delay=%d reg1=0x%08x reg2=0x%08x\n",
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delay, reg1_val, reg2_val);
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if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
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reg = cx_read(PAD_CTRL);
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/* Set TS1_OE */
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@ -1475,7 +1534,6 @@ static int cx23885_stop_dma(struct cx23885_tsport *port)
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cx_write(PAD_CTRL, reg);
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cx_write(port->reg_src_sel, 0);
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cx_write(port->reg_gen_ctrl, 8);
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}
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if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
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@ -288,6 +288,18 @@ Channel manager Data Structure entry = 20 DWORD
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#define AUDIO_EXT_INT_MSTAT 0x00040068
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#define AUDIO_EXT_INT_SSTAT 0x0004006C
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/* Bits [7:0] set in both TC_REQ and TC_REQ_SET
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* indicate a stall in the RISC engine for a
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* particular rider traffic class. This causes
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* the 885 and 888 bridges (unknown about 887)
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* to become inoperable. Setting bits in
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* TC_REQ_SET resets the corresponding bits
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* in TC_REQ (and TC_REQ_SET) allowing
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* operation to continue.
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*/
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#define TC_REQ 0x00040090
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#define TC_REQ_SET 0x00040094
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#define RDR_CFG0 0x00050000
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#define RDR_CFG1 0x00050004
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#define RDR_CFG2 0x00050008
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@ -386,6 +398,8 @@ Channel manager Data Structure entry = 20 DWORD
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#define VID_B_PIXEL_FRMT 0x00130184
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/* Video C Interface */
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#define VID_C_DMA 0x00130200
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#define VBI_C_DMA 0x00130208
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#define VID_C_GPCNT 0x00130220
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#define VID_C_GPCNT_CTL 0x00130230
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#define VBI_C_GPCNT_CTL 0x00130234
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