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PCI: rockchip: Separate common code from RC driver
In preparation for introducing EP driver for Rockchip PCIe controller, rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of RC driver and EP driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
This commit is contained in:
Shawn Lin
Lorenzo Pieralisi
parent
60cc43fc88
commit
956cd99b35
@ -10940,8 +10940,8 @@ M: Shawn Lin <shawn.lin@rock-chips.com>
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L: linux-pci@vger.kernel.org
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L: linux-rockchip@lists.infradead.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt
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F: drivers/pci/host/pcie-rockchip.c
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F: Documentation/devicetree/bindings/pci/rockchip-pcie*
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F: drivers/pci/host/pcie-rockchip*
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PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC
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M: Linus Walleij <linus.walleij@linaro.org>
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@ -179,11 +179,16 @@ config PCI_HOST_THUNDER_ECAM
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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config PCIE_ROCKCHIP
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tristate "Rockchip PCIe controller"
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bool
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depends on PCI
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config PCIE_ROCKCHIP_HOST
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tristate "Rockchip PCIe host controller"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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depends on OF
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depends on PCI_MSI_IRQ_DOMAIN
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select MFD_SYSCON
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select PCIE_ROCKCHIP
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help
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Say Y here if you want internal PCI support on Rockchip SoC.
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There is 1 internal PCIe port available to support GEN2 with
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@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
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obj-$(CONFIG_VMD) += vmd.o
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1368
drivers/pci/host/pcie-rockchip-host.c
Normal file
1368
drivers/pci/host/pcie-rockchip-host.c
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
245
drivers/pci/host/pcie-rockchip.h
Normal file
245
drivers/pci/host/pcie-rockchip.h
Normal file
@ -0,0 +1,245 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip AXI PCIe controller driver
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*
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* Copyright (c) 2018 Rockchip, Inc.
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*
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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*
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*/
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#ifndef _PCIE_ROCKCHIP_H
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#define _PCIE_ROCKCHIP_H
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#include <linux/kernel.h>
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#include <linux/pci.h>
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/*
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* The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
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* bits. This allows atomic updates of the register without locking.
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*/
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
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#define MAX_LANE_NUM 4
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#define PCIE_CLIENT_BASE 0x0
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#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
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#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
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#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
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#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
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#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
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#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
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#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
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#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
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#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
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#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
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#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
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#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19
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#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
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#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
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#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
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#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
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#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
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#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
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#define PCIE_CLIENT_INTR_SHIFT 5
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#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
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#define PCIE_CLIENT_INT_MSG BIT(14)
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#define PCIE_CLIENT_INT_HOT_RST BIT(13)
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#define PCIE_CLIENT_INT_DPA BIT(12)
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#define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
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#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
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#define PCIE_CLIENT_INT_CORR_ERR BIT(9)
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#define PCIE_CLIENT_INT_INTD BIT(8)
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#define PCIE_CLIENT_INT_INTC BIT(7)
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#define PCIE_CLIENT_INT_INTB BIT(6)
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#define PCIE_CLIENT_INT_INTA BIT(5)
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#define PCIE_CLIENT_INT_LOCAL BIT(4)
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#define PCIE_CLIENT_INT_UDMA BIT(3)
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#define PCIE_CLIENT_INT_PHY BIT(2)
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#define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
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#define PCIE_CLIENT_INT_PWR_STCG BIT(0)
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#define PCIE_CLIENT_INT_LEGACY \
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(PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
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PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
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#define PCIE_CLIENT_INT_CLI \
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(PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
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PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
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PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
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PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
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PCIE_CLIENT_INT_PHY)
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#define PCIE_CORE_CTRL_MGMT_BASE 0x900000
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#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
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#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
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#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
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#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
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#define PCIE_CORE_PL_CONF_LANE_SHIFT 1
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#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
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#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
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#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
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#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
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#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
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#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
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#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
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#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
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(((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
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#define PCIE_CORE_LANE_MAP (PCIE_CORE_CTRL_MGMT_BASE + 0x200)
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#define PCIE_CORE_LANE_MAP_MASK 0x0000000f
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#define PCIE_CORE_LANE_MAP_REVERSE BIT(16)
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#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
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#define PCIE_CORE_INT_PRFPE BIT(0)
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#define PCIE_CORE_INT_CRFPE BIT(1)
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#define PCIE_CORE_INT_RRPE BIT(2)
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#define PCIE_CORE_INT_PRFO BIT(3)
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#define PCIE_CORE_INT_CRFO BIT(4)
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#define PCIE_CORE_INT_RT BIT(5)
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#define PCIE_CORE_INT_RTR BIT(6)
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#define PCIE_CORE_INT_PE BIT(7)
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#define PCIE_CORE_INT_MTR BIT(8)
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#define PCIE_CORE_INT_UCR BIT(9)
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#define PCIE_CORE_INT_FCE BIT(10)
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#define PCIE_CORE_INT_CT BIT(11)
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#define PCIE_CORE_INT_UTC BIT(18)
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#define PCIE_CORE_INT_MMVC BIT(19)
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#define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44)
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#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
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#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
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#define PCIE_CORE_INT \
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(PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
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PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
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PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
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PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
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PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
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PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
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PCIE_CORE_INT_MMVC)
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#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
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#define PCIE_RC_CONFIG_BASE 0xa00000
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#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
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#define PCIE_RC_CONFIG_SCC_SHIFT 16
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
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#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5)
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#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5)
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#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
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#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
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#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
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#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
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#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
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#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
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#define PCIE_CORE_AXI_CONF_BASE 0xc00000
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#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
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#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
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#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
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#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
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#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
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#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
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#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
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#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
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#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
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#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
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#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
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/* Size of one AXI Region (not Region 0) */
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#define AXI_REGION_SIZE BIT(20)
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/* Size of Region 0, equal to sum of sizes of other regions */
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#define AXI_REGION_0_SIZE (32 * (0x1 << 20))
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#define OB_REG_SIZE_SHIFT 5
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#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
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#define AXI_WRAPPER_IO_WRITE 0x6
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#define AXI_WRAPPER_MEM_WRITE 0x2
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#define AXI_WRAPPER_TYPE0_CFG 0xa
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#define AXI_WRAPPER_TYPE1_CFG 0xb
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#define AXI_WRAPPER_NOR_MSG 0xc
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#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
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#define MIN_AXI_ADDR_BITS_PASSED 8
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#define PCIE_RC_SEND_PME_OFF 0x11960
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#define ROCKCHIP_VENDOR_ID 0x1d87
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#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
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#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
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#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
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#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
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#define PCIE_ECAM_ADDR(bus, dev, func, reg) \
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(PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
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PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
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#define PCIE_LINK_IS_L2(x) \
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(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
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#define PCIE_LINK_UP(x) \
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(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
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#define PCIE_LINK_IS_GEN2(x) \
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(((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G)
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#define RC_REGION_0_ADDR_TRANS_H 0x00000000
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#define RC_REGION_0_ADDR_TRANS_L 0x00000000
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#define RC_REGION_0_PASS_BITS (25 - 1)
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#define RC_REGION_0_TYPE_MASK GENMASK(3, 0)
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#define MAX_AXI_WRAPPER_REGION_NUM 33
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struct rockchip_pcie {
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void __iomem *reg_base; /* DT axi-base */
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void __iomem *apb_base; /* DT apb-base */
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bool legacy_phy;
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struct phy *phys[MAX_LANE_NUM];
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struct reset_control *core_rst;
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struct reset_control *mgmt_rst;
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struct reset_control *mgmt_sticky_rst;
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struct reset_control *pipe_rst;
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struct reset_control *pm_rst;
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struct reset_control *aclk_rst;
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struct reset_control *pclk_rst;
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struct clk *aclk_pcie;
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struct clk *aclk_perf_pcie;
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struct clk *hclk_pcie;
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struct clk *clk_pcie_pm;
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struct regulator *vpcie12v; /* 12V power supply */
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struct regulator *vpcie3v3; /* 3.3V power supply */
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struct regulator *vpcie1v8; /* 1.8V power supply */
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struct regulator *vpcie0v9; /* 0.9V power supply */
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struct gpio_desc *ep_gpio;
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u32 lanes;
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u8 lanes_map;
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u8 root_bus_nr;
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int link_gen;
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struct device *dev;
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struct irq_domain *irq_domain;
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int offset;
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struct pci_bus *root_bus;
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struct resource *io;
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phys_addr_t io_bus_addr;
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u32 io_size;
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void __iomem *msg_region;
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u32 mem_size;
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phys_addr_t msg_bus_addr;
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phys_addr_t mem_bus_addr;
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};
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static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
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{
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return readl(rockchip->apb_base + reg);
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}
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static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
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u32 reg)
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{
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writel(val, rockchip->apb_base + reg);
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}
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int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
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void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
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int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
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void rockchip_pcie_disable_clocks(void *data);
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void rockchip_pcie_cfg_configuration_accesses(
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struct rockchip_pcie *rockchip, u32 type);
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#endif /* _PCIE_ROCKCHIP_H */
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