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ASoC: tegra: Add routes for few AHUB modules

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Add routing support for following modules of AHUB:
 * SFC (Sampling Frequency Converter)
 * MVC (Master Volume Control)
 * AMX (Audio Multiplexer)
 * ADX (Audio Demultiplexer)
 * Mixer

These modules can be plugged into audio path as per the need using
routing controls similar to the already existing routes to I/O modules
such as I2S, DMIC and DSPK.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Link: https://lore.kernel.org/r/1631551342-25469-6-git-send-email-spujar@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sameer Pujar 2021-09-13 22:12:13 +05:30 committed by Mark Brown
parent aa56a9dedf
commit 94d486c2e5
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 509 additions and 2 deletions
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511
sound/soc/tegra/tegra210_ahub.c
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@ -105,14 +105,68 @@ static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
DAI(ADMAIF8),
DAI(ADMAIF9),
DAI(ADMAIF10),
/* XBAR <-> I2S <-> Codec */
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
/* XBAR <- DMIC <- Codec */
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
/* XBAR -> SFC -> XBAR */
DAI(SFC1 RX),
DAI(SFC1 TX),
DAI(SFC2 RX),
DAI(SFC2 TX),
DAI(SFC3 RX),
DAI(SFC3 TX),
DAI(SFC4 RX),
DAI(SFC4 TX),
/* XBAR -> MVC -> XBAR */
DAI(MVC1 RX),
DAI(MVC1 TX),
DAI(MVC2 RX),
DAI(MVC2 TX),
/* XBAR -> AMX(4:1) -> XBAR */
DAI(AMX1 RX1),
DAI(AMX1 RX2),
DAI(AMX1 RX3),
DAI(AMX1 RX4),
DAI(AMX1),
DAI(AMX2 RX1),
DAI(AMX2 RX2),
DAI(AMX2 RX3),
DAI(AMX2 RX4),
DAI(AMX2),
/* XBAR -> ADX(1:4) -> XBAR */
DAI(ADX1),
DAI(ADX1 TX1),
DAI(ADX1 TX2),
DAI(ADX1 TX3),
DAI(ADX1 TX4),
DAI(ADX2),
DAI(ADX2 TX1),
DAI(ADX2 TX2),
DAI(ADX2 TX3),
DAI(ADX2 TX4),
/* XBAR -> MIXER(10:5) -> XBAR */
DAI(MIXER1 RX1),
DAI(MIXER1 RX2),
DAI(MIXER1 RX3),
DAI(MIXER1 RX4),
DAI(MIXER1 RX5),
DAI(MIXER1 RX6),
DAI(MIXER1 RX7),
DAI(MIXER1 RX8),
DAI(MIXER1 RX9),
DAI(MIXER1 RX10),
DAI(MIXER1 TX1),
DAI(MIXER1 TX2),
DAI(MIXER1 TX3),
DAI(MIXER1 TX4),
DAI(MIXER1 TX5),
};
static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
@ -136,18 +190,93 @@ static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
DAI(ADMAIF18),
DAI(ADMAIF19),
DAI(ADMAIF20),
/* XBAR <-> I2S <-> Codec */
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
DAI(I2S6),
/* XBAR <- DMIC <- Codec */
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
DAI(DMIC4),
/* XBAR -> DSPK -> Codec */
DAI(DSPK1),
DAI(DSPK2),
/* XBAR -> SFC -> XBAR */
DAI(SFC1 RX),
DAI(SFC1 TX),
DAI(SFC2 RX),
DAI(SFC2 TX),
DAI(SFC3 RX),
DAI(SFC3 TX),
DAI(SFC4 RX),
DAI(SFC4 TX),
/* XBAR -> MVC -> XBAR */
DAI(MVC1 RX),
DAI(MVC1 TX),
DAI(MVC2 RX),
DAI(MVC2 TX),
/* XBAR -> AMX(4:1) -> XBAR */
DAI(AMX1 RX1),
DAI(AMX1 RX2),
DAI(AMX1 RX3),
DAI(AMX1 RX4),
DAI(AMX1),
DAI(AMX2 RX1),
DAI(AMX2 RX2),
DAI(AMX2 RX3),
DAI(AMX2 RX4),
DAI(AMX2),
DAI(AMX3 RX1),
DAI(AMX3 RX2),
DAI(AMX3 RX3),
DAI(AMX3 RX4),
DAI(AMX3),
DAI(AMX4 RX1),
DAI(AMX4 RX2),
DAI(AMX4 RX3),
DAI(AMX4 RX4),
DAI(AMX4),
/* XBAR -> ADX(1:4) -> XBAR */
DAI(ADX1),
DAI(ADX1 TX1),
DAI(ADX1 TX2),
DAI(ADX1 TX3),
DAI(ADX1 TX4),
DAI(ADX2),
DAI(ADX2 TX1),
DAI(ADX2 TX2),
DAI(ADX2 TX3),
DAI(ADX2 TX4),
DAI(ADX3),
DAI(ADX3 TX1),
DAI(ADX3 TX2),
DAI(ADX3 TX3),
DAI(ADX3 TX4),
DAI(ADX4),
DAI(ADX4 TX1),
DAI(ADX4 TX2),
DAI(ADX4 TX3),
DAI(ADX4 TX4),
/* XBAR -> MIXER1(10:5) -> XBAR */
DAI(MIXER1 RX1),
DAI(MIXER1 RX2),
DAI(MIXER1 RX3),
DAI(MIXER1 RX4),
DAI(MIXER1 RX5),
DAI(MIXER1 RX6),
DAI(MIXER1 RX7),
DAI(MIXER1 RX8),
DAI(MIXER1 RX9),
DAI(MIXER1 RX10),
DAI(MIXER1 TX1),
DAI(MIXER1 TX2),
DAI(MIXER1 TX3),
DAI(MIXER1 TX4),
DAI(MIXER1 TX5),
};
static const char * const tegra210_ahub_mux_texts[] = {
@ -170,6 +299,27 @@ static const char * const tegra210_ahub_mux_texts[] = {
"DMIC1",
"DMIC2",
"DMIC3",
"SFC1",
"SFC2",
"SFC3",
"SFC4",
"MVC1",
"MVC2",
"AMX1",
"AMX2",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
};
static const char * const tegra186_ahub_mux_texts[] = {
@ -204,10 +354,42 @@ static const char * const tegra186_ahub_mux_texts[] = {
"DMIC2",
"DMIC3",
"DMIC4",
"SFC1",
"SFC2",
"SFC3",
"SFC4",
"MVC1",
"MVC2",
"AMX1",
"AMX2",
"AMX3",
"AMX4",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"ADX3 TX1",
"ADX3 TX2",
"ADX3 TX3",
"ADX3 TX4",
"ADX4 TX1",
"ADX4 TX2",
"ADX4 TX3",
"ADX4 TX4",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
};
static const unsigned int tegra210_ahub_mux_values[] = {
0,
/* ADMAIF */
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
@ -218,18 +400,47 @@ static const unsigned int tegra210_ahub_mux_values[] = {
MUX_VALUE(0, 7),
MUX_VALUE(0, 8),
MUX_VALUE(0, 9),
/* I2S */
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
/* DMIC */
MUX_VALUE(2, 18),
MUX_VALUE(2, 19),
MUX_VALUE(2, 20),
/* SFC */
MUX_VALUE(0, 24),
MUX_VALUE(0, 25),
MUX_VALUE(0, 26),
MUX_VALUE(0, 27),
/* MVC */
MUX_VALUE(2, 8),
MUX_VALUE(2, 9),
/* AMX */
MUX_VALUE(1, 8),
MUX_VALUE(1, 9),
/* ADX */
MUX_VALUE(2, 24),
MUX_VALUE(2, 25),
MUX_VALUE(2, 26),
MUX_VALUE(2, 27),
MUX_VALUE(2, 28),
MUX_VALUE(2, 29),
MUX_VALUE(2, 30),
MUX_VALUE(2, 31),
/* MIXER */
MUX_VALUE(1, 0),
MUX_VALUE(1, 1),
MUX_VALUE(1, 2),
MUX_VALUE(1, 3),
MUX_VALUE(1, 4),
};
static const unsigned int tegra186_ahub_mux_values[] = {
0,
/* ADMAIF */
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
@ -246,20 +457,59 @@ static const unsigned int tegra186_ahub_mux_values[] = {
MUX_VALUE(0, 13),
MUX_VALUE(0, 14),
MUX_VALUE(0, 15),
/* I2S */
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
MUX_VALUE(0, 21),
/* ADMAIF */
MUX_VALUE(3, 16),
MUX_VALUE(3, 17),
MUX_VALUE(3, 18),
MUX_VALUE(3, 19),
/* DMIC */
MUX_VALUE(2, 18),
MUX_VALUE(2, 19),
MUX_VALUE(2, 20),
MUX_VALUE(2, 21),
/* SFC */
MUX_VALUE(0, 24),
MUX_VALUE(0, 25),
MUX_VALUE(0, 26),
MUX_VALUE(0, 27),
/* MVC */
MUX_VALUE(2, 8),
MUX_VALUE(2, 9),
/* AMX */
MUX_VALUE(1, 8),
MUX_VALUE(1, 9),
MUX_VALUE(1, 10),
MUX_VALUE(1, 11),
/* ADX */
MUX_VALUE(2, 24),
MUX_VALUE(2, 25),
MUX_VALUE(2, 26),
MUX_VALUE(2, 27),
MUX_VALUE(2, 28),
MUX_VALUE(2, 29),
MUX_VALUE(2, 30),
MUX_VALUE(2, 31),
MUX_VALUE(3, 0),
MUX_VALUE(3, 1),
MUX_VALUE(3, 2),
MUX_VALUE(3, 3),
MUX_VALUE(3, 4),
MUX_VALUE(3, 5),
MUX_VALUE(3, 6),
MUX_VALUE(3, 7),
/* MIXER */
MUX_VALUE(1, 0),
MUX_VALUE(1, 1),
MUX_VALUE(1, 2),
MUX_VALUE(1, 3),
MUX_VALUE(1, 4),
};
/* Controls for t210 */
@ -278,6 +528,32 @@ MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18);
MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19);
MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a);
MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b);
MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48);
MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49);
MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50);
MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51);
MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52);
MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53);
MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54);
MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55);
MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56);
MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57);
MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58);
MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59);
MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20);
MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21);
MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22);
MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23);
MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24);
MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25);
MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
/* Controls for t186 */
MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
@ -308,6 +584,42 @@ MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18);
MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19);
MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a);
MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b);
MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48);
MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49);
MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50);
MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51);
MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52);
MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53);
MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54);
MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55);
MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56);
MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57);
MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58);
MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59);
MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a);
MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b);
MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64);
MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65);
MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66);
MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67);
MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60);
MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61);
MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62);
MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63);
MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20);
MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21);
MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22);
MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23);
MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24);
MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25);
MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26);
MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
/*
* The number of entries in, and order of, this array is closely tied to the
@ -333,6 +645,47 @@ static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
WIDGETS("SFC1", t210_sfc1_tx),
WIDGETS("SFC2", t210_sfc2_tx),
WIDGETS("SFC3", t210_sfc3_tx),
WIDGETS("SFC4", t210_sfc4_tx),
WIDGETS("MVC1", t210_mvc1_tx),
WIDGETS("MVC2", t210_mvc2_tx),
WIDGETS("AMX1 RX1", t210_amx11_tx),
WIDGETS("AMX1 RX2", t210_amx12_tx),
WIDGETS("AMX1 RX3", t210_amx13_tx),
WIDGETS("AMX1 RX4", t210_amx14_tx),
WIDGETS("AMX2 RX1", t210_amx21_tx),
WIDGETS("AMX2 RX2", t210_amx22_tx),
WIDGETS("AMX2 RX3", t210_amx23_tx),
WIDGETS("AMX2 RX4", t210_amx24_tx),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
WIDGETS("ADX1", t210_adx1_tx),
WIDGETS("ADX2", t210_adx2_tx),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
WIDGETS("MIXER1 RX1", t210_mixer11_tx),
WIDGETS("MIXER1 RX2", t210_mixer12_tx),
WIDGETS("MIXER1 RX3", t210_mixer13_tx),
WIDGETS("MIXER1 RX4", t210_mixer14_tx),
WIDGETS("MIXER1 RX5", t210_mixer15_tx),
WIDGETS("MIXER1 RX6", t210_mixer16_tx),
WIDGETS("MIXER1 RX7", t210_mixer17_tx),
WIDGETS("MIXER1 RX8", t210_mixer18_tx),
WIDGETS("MIXER1 RX9", t210_mixer19_tx),
WIDGETS("MIXER1 RX10", t210_mixer110_tx),
TX_WIDGETS("MIXER1 TX1"),
TX_WIDGETS("MIXER1 TX2"),
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
};
static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
@ -368,6 +721,67 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
TX_WIDGETS("DMIC4"),
WIDGETS("DSPK1", t186_dspk1_tx),
WIDGETS("DSPK2", t186_dspk2_tx),
WIDGETS("SFC1", t186_sfc1_tx),
WIDGETS("SFC2", t186_sfc2_tx),
WIDGETS("SFC3", t186_sfc3_tx),
WIDGETS("SFC4", t186_sfc4_tx),
WIDGETS("MVC1", t186_mvc1_tx),
WIDGETS("MVC2", t186_mvc2_tx),
WIDGETS("AMX1 RX1", t186_amx11_tx),
WIDGETS("AMX1 RX2", t186_amx12_tx),
WIDGETS("AMX1 RX3", t186_amx13_tx),
WIDGETS("AMX1 RX4", t186_amx14_tx),
WIDGETS("AMX2 RX1", t186_amx21_tx),
WIDGETS("AMX2 RX2", t186_amx22_tx),
WIDGETS("AMX2 RX3", t186_amx23_tx),
WIDGETS("AMX2 RX4", t186_amx24_tx),
WIDGETS("AMX3 RX1", t186_amx31_tx),
WIDGETS("AMX3 RX2", t186_amx32_tx),
WIDGETS("AMX3 RX3", t186_amx33_tx),
WIDGETS("AMX3 RX4", t186_amx34_tx),
WIDGETS("AMX4 RX1", t186_amx41_tx),
WIDGETS("AMX4 RX2", t186_amx42_tx),
WIDGETS("AMX4 RX3", t186_amx43_tx),
WIDGETS("AMX4 RX4", t186_amx44_tx),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
TX_WIDGETS("AMX3"),
TX_WIDGETS("AMX4"),
WIDGETS("ADX1", t186_adx1_tx),
WIDGETS("ADX2", t186_adx2_tx),
WIDGETS("ADX3", t186_adx3_tx),
WIDGETS("ADX4", t186_adx4_tx),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
TX_WIDGETS("ADX3 TX1"),
TX_WIDGETS("ADX3 TX2"),
TX_WIDGETS("ADX3 TX3"),
TX_WIDGETS("ADX3 TX4"),
TX_WIDGETS("ADX4 TX1"),
TX_WIDGETS("ADX4 TX2"),
TX_WIDGETS("ADX4 TX3"),
TX_WIDGETS("ADX4 TX4"),
WIDGETS("MIXER1 RX1", t186_mixer11_tx),
WIDGETS("MIXER1 RX2", t186_mixer12_tx),
WIDGETS("MIXER1 RX3", t186_mixer13_tx),
WIDGETS("MIXER1 RX4", t186_mixer14_tx),
WIDGETS("MIXER1 RX5", t186_mixer15_tx),
WIDGETS("MIXER1 RX6", t186_mixer16_tx),
WIDGETS("MIXER1 RX7", t186_mixer17_tx),
WIDGETS("MIXER1 RX8", t186_mixer18_tx),
WIDGETS("MIXER1 RX9", t186_mixer19_tx),
WIDGETS("MIXER1 RX10", t186_mixer110_tx),
TX_WIDGETS("MIXER1 TX1"),
TX_WIDGETS("MIXER1 TX2"),
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
};
#define TEGRA_COMMON_MUX_ROUTES(name) \
@ -389,7 +803,28 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
{ name " Mux", "I2S5", "I2S5 XBAR-RX" }, \
{ name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \
{ name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \
{ name " Mux", "DMIC3", "DMIC3 XBAR-RX" },
{ name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \
{ name " Mux", "SFC1", "SFC1 XBAR-RX" }, \
{ name " Mux", "SFC2", "SFC2 XBAR-RX" }, \
{ name " Mux", "SFC3", "SFC3 XBAR-RX" }, \
{ name " Mux", "SFC4", "SFC4 XBAR-RX" }, \
{ name " Mux", "MVC1", "MVC1 XBAR-RX" }, \
{ name " Mux", "MVC2", "MVC2 XBAR-RX" }, \
{ name " Mux", "AMX1", "AMX1 XBAR-RX" }, \
{ name " Mux", "AMX2", "AMX2 XBAR-RX" }, \
{ name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \
{ name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \
{ name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \
{ name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \
{ name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \
{ name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \
{ name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \
{ name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" },
#define TEGRA186_ONLY_MUX_ROUTES(name) \
{ name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \
@ -403,7 +838,17 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
{ name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \
{ name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \
{ name " Mux", "I2S6", "I2S6 XBAR-RX" }, \
{ name " Mux", "DMIC4", "DMIC4 XBAR-RX" },
{ name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \
{ name " Mux", "AMX3", "AMX3 XBAR-RX" }, \
{ name " Mux", "AMX4", "AMX4 XBAR-RX" }, \
{ name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \
{ name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \
{ name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \
{ name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \
{ name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \
{ name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \
{ name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \
{ name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" },
#define TEGRA210_MUX_ROUTES(name) \
TEGRA_COMMON_MUX_ROUTES(name)
@ -450,6 +895,32 @@ static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
TEGRA210_MUX_ROUTES("I2S3")
TEGRA210_MUX_ROUTES("I2S4")
TEGRA210_MUX_ROUTES("I2S5")
TEGRA210_MUX_ROUTES("SFC1")
TEGRA210_MUX_ROUTES("SFC2")
TEGRA210_MUX_ROUTES("SFC3")
TEGRA210_MUX_ROUTES("SFC4")
TEGRA210_MUX_ROUTES("MVC1")
TEGRA210_MUX_ROUTES("MVC2")
TEGRA210_MUX_ROUTES("AMX1 RX1")
TEGRA210_MUX_ROUTES("AMX1 RX2")
TEGRA210_MUX_ROUTES("AMX1 RX3")
TEGRA210_MUX_ROUTES("AMX1 RX4")
TEGRA210_MUX_ROUTES("AMX2 RX1")
TEGRA210_MUX_ROUTES("AMX2 RX2")
TEGRA210_MUX_ROUTES("AMX2 RX3")
TEGRA210_MUX_ROUTES("AMX2 RX4")
TEGRA210_MUX_ROUTES("ADX1")
TEGRA210_MUX_ROUTES("ADX2")
TEGRA210_MUX_ROUTES("MIXER1 RX1")
TEGRA210_MUX_ROUTES("MIXER1 RX2")
TEGRA210_MUX_ROUTES("MIXER1 RX3")
TEGRA210_MUX_ROUTES("MIXER1 RX4")
TEGRA210_MUX_ROUTES("MIXER1 RX5")
TEGRA210_MUX_ROUTES("MIXER1 RX6")
TEGRA210_MUX_ROUTES("MIXER1 RX7")
TEGRA210_MUX_ROUTES("MIXER1 RX8")
TEGRA210_MUX_ROUTES("MIXER1 RX9")
TEGRA210_MUX_ROUTES("MIXER1 RX10")
};
static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
@ -501,6 +972,42 @@ static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
TEGRA186_MUX_ROUTES("I2S6")
TEGRA186_MUX_ROUTES("DSPK1")
TEGRA186_MUX_ROUTES("DSPK2")
TEGRA186_MUX_ROUTES("SFC1")
TEGRA186_MUX_ROUTES("SFC2")
TEGRA186_MUX_ROUTES("SFC3")
TEGRA186_MUX_ROUTES("SFC4")
TEGRA186_MUX_ROUTES("MVC1")
TEGRA186_MUX_ROUTES("MVC2")
TEGRA186_MUX_ROUTES("AMX1 RX1")
TEGRA186_MUX_ROUTES("AMX1 RX2")
TEGRA186_MUX_ROUTES("AMX1 RX3")
TEGRA186_MUX_ROUTES("AMX1 RX4")
TEGRA186_MUX_ROUTES("AMX2 RX1")
TEGRA186_MUX_ROUTES("AMX2 RX2")
TEGRA186_MUX_ROUTES("AMX2 RX3")
TEGRA186_MUX_ROUTES("AMX2 RX4")
TEGRA186_MUX_ROUTES("AMX3 RX1")
TEGRA186_MUX_ROUTES("AMX3 RX2")
TEGRA186_MUX_ROUTES("AMX3 RX3")
TEGRA186_MUX_ROUTES("AMX3 RX4")
TEGRA186_MUX_ROUTES("AMX4 RX1")
TEGRA186_MUX_ROUTES("AMX4 RX2")
TEGRA186_MUX_ROUTES("AMX4 RX3")
TEGRA186_MUX_ROUTES("AMX4 RX4")
TEGRA186_MUX_ROUTES("ADX1")
TEGRA186_MUX_ROUTES("ADX2")
TEGRA186_MUX_ROUTES("ADX3")
TEGRA186_MUX_ROUTES("ADX4")
TEGRA186_MUX_ROUTES("MIXER1 RX1")
TEGRA186_MUX_ROUTES("MIXER1 RX2")
TEGRA186_MUX_ROUTES("MIXER1 RX3")
TEGRA186_MUX_ROUTES("MIXER1 RX4")
TEGRA186_MUX_ROUTES("MIXER1 RX5")
TEGRA186_MUX_ROUTES("MIXER1 RX6")
TEGRA186_MUX_ROUTES("MIXER1 RX7")
TEGRA186_MUX_ROUTES("MIXER1 RX8")
TEGRA186_MUX_ROUTES("MIXER1 RX9")
TEGRA186_MUX_ROUTES("MIXER1 RX10")
};
static const struct snd_soc_component_driver tegra210_ahub_component = {