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arm64: add FEAT_LSE128 HWCAP
Add HWCAP for FEAT_LSE128 (128-bit Atomic instructions). Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20231003124544.858804-2-joey.gouly@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -314,6 +314,9 @@ HWCAP2_SVE_B16B16
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HWCAP2_LRCPC3
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Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
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HWCAP2_LSE128
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Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
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4. Unused AT_HWCAP bits
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-----------------------
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@ -141,6 +141,7 @@
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#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC)
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#define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16)
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#define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3)
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#define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128)
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/*
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* This yields a mask that user programs can use to figure out what
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@ -106,5 +106,6 @@
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#define HWCAP2_HBC (1UL << 44)
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#define HWCAP2_SVE_B16B16 (1UL << 45)
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#define HWCAP2_LRCPC3 (1UL << 46)
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#define HWCAP2_LSE128 (1UL << 47)
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -2789,6 +2789,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
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HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
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HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
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HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128),
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HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
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HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
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HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
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@ -129,6 +129,7 @@ static const char *const hwcap_str[] = {
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[KERNEL_HWCAP_HBC] = "hbc",
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[KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
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[KERNEL_HWCAP_LRCPC3] = "lrcpc3",
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[KERNEL_HWCAP_LSE128] = "lse128",
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};
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#ifdef CONFIG_COMPAT
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@ -1239,6 +1239,7 @@ EndEnum
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UnsignedEnum 23:20 ATOMIC
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0b0000 NI
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0b0010 IMP
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0b0011 FEAT_LSE128
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EndEnum
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UnsignedEnum 19:16 CRC32
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0b0000 NI
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