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gpio: gpio-mm: Implement and utilize register structures
Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. The GPIO-MM device features an Intel 8255 compatible GPIO interface, so the i8255 GPIO module is selected and utilized as well. Tested-by: Fred Eckert <Frede@cmslaser.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
parent
3ce632fdd1
commit
949506dc60
@ -886,6 +886,7 @@ config GPIO_GPIO_MM
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tristate "Diamond Systems GPIO-MM GPIO support"
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depends on PC104
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select ISA_BUS_API
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select GPIO_I8255
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help
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Enables GPIO support for the Diamond Systems GPIO-MM and GPIO-MM-12.
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@ -6,8 +6,6 @@
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* This driver supports the following Diamond Systems devices: GPIO-MM and
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* GPIO-MM-12.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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@ -17,7 +15,10 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include "gpio-i8255.h"
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MODULE_IMPORT_NS(I8255);
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#define GPIOMM_EXTENT 8
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#define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
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@ -27,32 +28,26 @@ static unsigned int num_gpiomm;
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module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
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MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
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#define GPIOMM_NUM_PPI 2
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/**
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* struct gpiomm_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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* @chip: instance of the gpio_chip
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* @ppi_state: Programmable Peripheral Interface group states
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* @ppi: Programmable Peripheral Interface groups
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*/
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struct gpiomm_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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spinlock_t lock;
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void __iomem *base;
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struct i8255_state ppi_state[GPIOMM_NUM_PPI];
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struct i8255 __iomem *ppi;
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};
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static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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if (gpiommgpio->io_state[port] & mask)
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if (i8255_get_direction(gpiommgpio->ppi_state, offset))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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@ -62,35 +57,8 @@ static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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unsigned long flags;
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unsigned int control;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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gpiommgpio->io_state[io_port] |= 0xF0;
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gpiommgpio->control[control_port] |= BIT(3);
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} else {
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gpiommgpio->io_state[io_port] |= 0x0F;
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gpiommgpio->control[control_port] |= BIT(0);
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}
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} else {
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gpiommgpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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gpiommgpio->control[control_port] |= BIT(4);
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else
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gpiommgpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | gpiommgpio->control[control_port];
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iowrite8(control, gpiommgpio->base + 3 + control_port*4);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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i8255_direction_input(gpiommgpio->ppi, gpiommgpio->ppi_state, offset);
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return 0;
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}
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@ -99,44 +67,9 @@ static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned int control;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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gpiommgpio->io_state[io_port] &= 0x0F;
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gpiommgpio->control[control_port] &= ~BIT(3);
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} else {
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gpiommgpio->io_state[io_port] &= 0xF0;
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gpiommgpio->control[control_port] &= ~BIT(0);
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}
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} else {
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gpiommgpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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gpiommgpio->control[control_port] &= ~BIT(4);
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else
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gpiommgpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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gpiommgpio->out_state[io_port] |= mask;
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else
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gpiommgpio->out_state[io_port] &= ~mask;
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control = BIT(7) | gpiommgpio->control[control_port];
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iowrite8(control, gpiommgpio->base + 3 + control_port*4);
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iowrite8(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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i8255_direction_output(gpiommgpio->ppi, gpiommgpio->ppi_state, offset,
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value);
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return 0;
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}
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@ -144,47 +77,16 @@ static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
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static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned int port_state;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(gpiommgpio->io_state[port] & mask)) {
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return -EINVAL;
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}
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port_state = ioread8(gpiommgpio->base + in_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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return !!(port_state & mask);
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return i8255_get(gpiommgpio->ppi, offset);
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}
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static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
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static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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void __iomem *port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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port_addr = gpiommgpio->base + ports[offset / 8];
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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i8255_get_multiple(gpiommgpio->ppi, mask, bits, chip->ngpio);
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return 0;
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}
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@ -193,49 +95,17 @@ static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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const unsigned int port = offset / 8;
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const unsigned int mask = BIT(offset % 8);
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const unsigned int out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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if (value)
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gpiommgpio->out_state[port] |= mask;
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else
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gpiommgpio->out_state[port] &= ~mask;
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iowrite8(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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i8255_set(gpiommgpio->ppi, gpiommgpio->ppi_state, offset, value);
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}
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static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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void __iomem *port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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port_addr = gpiommgpio->base + ports[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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spin_lock_irqsave(&gpiommgpio->lock, flags);
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/* update output state data and set device gpio register */
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gpiommgpio->out_state[index] &= ~gpio_mask;
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gpiommgpio->out_state[index] |= bitmask;
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iowrite8(gpiommgpio->out_state[index], port_addr);
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spin_unlock_irqrestore(&gpiommgpio->lock, flags);
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}
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i8255_set_multiple(gpiommgpio->ppi, gpiommgpio->ppi_state, mask, bits,
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chip->ngpio);
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}
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#define GPIOMM_NGPIO 48
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@ -250,6 +120,21 @@ static const char *gpiomm_names[GPIOMM_NGPIO] = {
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"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
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};
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static void gpiomm_init_dio(struct i8255 __iomem *const ppi,
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struct i8255_state *const ppi_state)
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{
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const unsigned long ngpio = 24;
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const unsigned long mask = GENMASK(ngpio - 1, 0);
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const unsigned long bits = 0;
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unsigned long i;
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/* Initialize all GPIO to output 0 */
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for (i = 0; i < GPIOMM_NUM_PPI; i++) {
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i8255_mode0_output(&ppi[i]);
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i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
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}
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}
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static int gpiomm_probe(struct device *dev, unsigned int id)
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{
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struct gpiomm_gpio *gpiommgpio;
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@ -266,8 +151,8 @@ static int gpiomm_probe(struct device *dev, unsigned int id)
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return -EBUSY;
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}
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gpiommgpio->base = devm_ioport_map(dev, base[id], GPIOMM_EXTENT);
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if (!gpiommgpio->base)
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gpiommgpio->ppi = devm_ioport_map(dev, base[id], GPIOMM_EXTENT);
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if (!gpiommgpio->ppi)
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return -ENOMEM;
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gpiommgpio->chip.label = name;
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@ -284,7 +169,8 @@ static int gpiomm_probe(struct device *dev, unsigned int id)
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gpiommgpio->chip.set = gpiomm_gpio_set;
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gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
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spin_lock_init(&gpiommgpio->lock);
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i8255_state_init(gpiommgpio->ppi_state, GPIOMM_NUM_PPI);
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gpiomm_init_dio(gpiommgpio->ppi, gpiommgpio->ppi_state);
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err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
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if (err) {
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@ -292,16 +178,6 @@ static int gpiomm_probe(struct device *dev, unsigned int id)
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return err;
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}
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/* initialize all GPIO as output */
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iowrite8(0x80, gpiommgpio->base + 3);
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iowrite8(0x00, gpiommgpio->base);
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iowrite8(0x00, gpiommgpio->base + 1);
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iowrite8(0x00, gpiommgpio->base + 2);
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iowrite8(0x80, gpiommgpio->base + 7);
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iowrite8(0x00, gpiommgpio->base + 4);
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iowrite8(0x00, gpiommgpio->base + 5);
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iowrite8(0x00, gpiommgpio->base + 6);
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return 0;
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}
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