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Merge branch 'mt7530-dsa-subdriver-improvements-act-iii'
says: ==================== MT7530 DSA Subdriver Improvements Act III This is the third patch series with the goal of simplifying the MT7530 DSA subdriver and improving support for MT7530, MT7531, and the switch on the MT7988 SoC. I have done a simple ping test to confirm basic communication on all switch ports on MCM and standalone MT7530, and MT7531 switch with this patch series applied. MT7621 Unielec, MCM MT7530: rgmii-only-gmac0-mt7621-unielec-u7621-06-16m.dtb gmac0-and-gmac1-mt7621-unielec-u7621-06-16m.dtb tftpboot 0x80008000 mips-uzImage.bin; tftpboot 0x83000000 mips-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootm 0x80008000 0x83000000 0x83f00000 MT7622 Bananapi, MT7531: gmac0-and-gmac1-mt7622-bananapi-bpi-r64.dtb tftpboot 0x40000000 arm64-Image; tftpboot 0x45000000 arm64-rootfs.cpio.uboot; tftpboot 0x4a000000 $dtb; booti 0x40000000 0x45000000 0x4a000000 MT7623 Bananapi, standalone MT7530: rgmii-only-gmac0-mt7623n-bananapi-bpi-r2.dtb gmac0-and-gmac1-mt7623n-bananapi-bpi-r2.dtb tftpboot 0x80008000 arm-zImage; tftpboot 0x83000000 arm-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootz 0x80008000 0x83000000 0x83f00000 This patch series is the continuation of the patch series linked below. https://lore.kernel.org/r/20230522121532.86610-1-arinc.unal@arinc9.com Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> --- Changes in v3: - Patch 8 - Explain properly the behaviour of setting link down on all ports at setup. - Split the changes for simplifying the link settings operations out to another patch. - Link to v2: https://lore.kernel.org/r/20240216-for-netnext-mt7530-improvements-3-v2-0-094cae3ff23b@arinc9.com Changes in v2: - Patch 8 - Use a single mt7530_rmw() instead of two mt7530_clear() and mt7530_set() commands. - Link to v1: https://lore.kernel.org/r/20240208-for-netnext-mt7530-improvements-3-v1-0-d7c1cfd502ca@arinc9.com ==================== Link: https://lore.kernel.org/r/20240301-for-netnext-mt7530-improvements-3-v3-0-449f4f166454@arinc9.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni
commit
9452c8b459
@ -966,18 +966,10 @@ mt753x_trap_frames(struct mt7530_priv *priv)
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MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));
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}
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static int
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static void
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mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
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{
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struct mt7530_priv *priv = ds->priv;
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int ret;
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/* Setup max capability of CPU port at first */
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if (priv->info->cpu_port_config) {
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ret = priv->info->cpu_port_config(ds, port);
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if (ret)
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return ret;
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}
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/* Enable Mediatek header mode on the cpu port */
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mt7530_write(priv, MT7530_PVC_P(port),
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@ -1003,8 +995,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
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/* Set to fallback mode for independent VLAN learning */
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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return 0;
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}
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static int
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@ -1028,7 +1018,6 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
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priv->ports[port].enable = true;
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
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priv->ports[port].pm);
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mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
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mutex_unlock(&priv->reg_mutex);
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@ -1048,7 +1037,6 @@ mt7530_port_disable(struct dsa_switch *ds, int port)
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priv->ports[port].enable = false;
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
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PCR_MATRIX_CLR);
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mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
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mutex_unlock(&priv->reg_mutex);
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}
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@ -2055,7 +2043,7 @@ mt7530_setup_irq(struct mt7530_priv *priv)
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}
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/* This register must be set for MT7530 to properly fire interrupts */
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if (priv->id != ID_MT7531)
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if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
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mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
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ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
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@ -2261,14 +2249,18 @@ mt7530_setup(struct dsa_switch *ds)
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val |= MHWTRAP_MANUAL;
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mt7530_write(priv, MT7530_MHWTRAP, val);
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priv->p6_interface = PHY_INTERFACE_MODE_NA;
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mt753x_trap_frames(priv);
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/* Enable and reset MIB counters */
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mt7530_mib_reset(ds);
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for (i = 0; i < MT7530_NUM_PORTS; i++) {
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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PMCR_FORCE_MODE, PMCR_FORCE_MODE);
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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PCR_MATRIX_CLR);
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@ -2277,9 +2269,7 @@ mt7530_setup(struct dsa_switch *ds)
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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if (dsa_is_cpu_port(ds, i)) {
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ret = mt753x_cpu_port_enable(ds, i);
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if (ret)
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return ret;
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mt753x_cpu_port_enable(ds, i);
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} else {
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mt7530_port_disable(ds, i);
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@ -2373,6 +2363,12 @@ mt7531_setup_common(struct dsa_switch *ds)
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UNU_FFP_MASK);
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for (i = 0; i < MT7530_NUM_PORTS; i++) {
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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MT7531_FORCE_MODE, MT7531_FORCE_MODE);
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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PCR_MATRIX_CLR);
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@ -2383,9 +2379,7 @@ mt7531_setup_common(struct dsa_switch *ds)
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mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
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if (dsa_is_cpu_port(ds, i)) {
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ret = mt753x_cpu_port_enable(ds, i);
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if (ret)
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return ret;
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mt753x_cpu_port_enable(ds, i);
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} else {
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mt7530_port_disable(ds, i);
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@ -2451,14 +2445,12 @@ mt7531_setup(struct dsa_switch *ds)
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val = mt7530_read(priv, MT7531_TOP_SIG_SR);
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priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
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/* all MACs must be forced link-down before sw reset */
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/* Force link down on all ports before internal reset */
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for (i = 0; i < MT7530_NUM_PORTS; i++)
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mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
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/* Reset the switch through internal reset */
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mt7530_write(priv, MT7530_SYS_CTRL,
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SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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SYS_CTRL_REG_RST);
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mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
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if (!priv->p5_sgmii) {
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mt7531_pll_setup(priv);
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@ -2476,10 +2468,6 @@ mt7531_setup(struct dsa_switch *ds)
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mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
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MT7531_GPIO0_INTERRUPT);
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/* Let phylink decide the interface later. */
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priv->p5_interface = PHY_INTERFACE_MODE_NA;
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priv->p6_interface = PHY_INTERFACE_MODE_NA;
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/* Enable PHY core PLL, since phy_device has not yet been created
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* provided for phy_[read,write]_mmd_indirect is called, we provide
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* our own mt7531_ind_mmd_phy_[read,write] to complete this
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@ -2589,7 +2577,7 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
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}
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}
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static int
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static void
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mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface)
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{
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@ -2599,22 +2587,14 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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mt7530_setup_port5(priv->ds, interface);
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else if (port == 6)
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mt7530_setup_port6(priv->ds, interface);
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return 0;
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}
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static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
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phy_interface_t interface,
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struct phy_device *phydev)
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static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
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phy_interface_t interface,
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struct phy_device *phydev)
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{
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u32 val;
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if (priv->p5_sgmii) {
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dev_err(priv->dev, "RGMII mode is not available for port %d\n",
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port);
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return -EINVAL;
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}
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val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
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val |= GP_CLK_EN;
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val &= ~GP_MODE_MASK;
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@ -2642,31 +2622,14 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
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case PHY_INTERFACE_MODE_RGMII_ID:
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break;
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default:
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return -EINVAL;
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break;
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}
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}
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mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
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return 0;
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}
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static bool mt753x_is_mac_port(u32 port)
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{
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return (port == 5 || port == 6);
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}
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static int
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mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface)
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{
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if (dsa_is_cpu_port(ds, port) &&
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interface == PHY_INTERFACE_MODE_INTERNAL)
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return 0;
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return -EINVAL;
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}
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static int
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static void
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mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface)
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{
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@ -2674,39 +2637,11 @@ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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struct phy_device *phydev;
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struct dsa_port *dp;
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if (!mt753x_is_mac_port(port)) {
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dev_err(priv->dev, "port %d is not a MAC port\n", port);
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return -EINVAL;
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}
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switch (interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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if (phy_interface_mode_is_rgmii(interface)) {
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dp = dsa_to_port(ds, port);
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phydev = dp->user->phydev;
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return mt7531_rgmii_setup(priv, port, interface, phydev);
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_NA:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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/* handled in SGMII PCS driver */
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return 0;
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default:
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return -EINVAL;
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mt7531_rgmii_setup(priv, port, interface, phydev);
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}
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return -EINVAL;
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}
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static int
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mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct mt7530_priv *priv = ds->priv;
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return priv->info->mac_port_config(ds, port, mode, state->interface);
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}
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static struct phylink_pcs *
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@ -2732,52 +2667,13 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct mt7530_priv *priv = ds->priv;
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u32 mcr_cur, mcr_new;
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switch (port) {
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case 0 ... 4:
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if (state->interface != PHY_INTERFACE_MODE_GMII &&
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state->interface != PHY_INTERFACE_MODE_INTERNAL)
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goto unsupported;
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break;
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case 5:
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if (priv->p5_interface == state->interface)
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break;
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if (mt753x_mac_config(ds, port, mode, state) < 0)
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goto unsupported;
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if (priv->p5_intf_sel != P5_DISABLED)
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priv->p5_interface = state->interface;
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break;
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case 6:
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if (priv->p6_interface == state->interface)
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break;
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if (mt753x_mac_config(ds, port, mode, state) < 0)
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goto unsupported;
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priv->p6_interface = state->interface;
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break;
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default:
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unsupported:
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dev_err(ds->dev, "%s: unsupported %s port: %i\n",
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__func__, phy_modes(state->interface), port);
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return;
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}
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mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
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mcr_new = mcr_cur;
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mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
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mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
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PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
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if ((port == 5 || port == 6) && priv->info->mac_port_config)
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priv->info->mac_port_config(ds, port, mode, state->interface);
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/* Are we connected to external phy */
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if (port == 5 && dsa_is_user_port(ds, 5))
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mcr_new |= PMCR_EXT_PHY;
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if (mcr_new != mcr_cur)
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mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
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mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
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}
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static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
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@ -2801,17 +2697,10 @@ static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
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mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
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/* MT753x MAC works in 1G full duplex mode for all up-clocked
|
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* variants.
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*/
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if (interface == PHY_INTERFACE_MODE_TRGMII ||
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(phy_interface_mode_is_8023z(interface))) {
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speed = SPEED_1000;
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duplex = DUPLEX_FULL;
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}
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switch (speed) {
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case SPEED_1000:
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case SPEED_2500:
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case SPEED_10000:
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mcr |= PMCR_FORCE_SPEED_1000;
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break;
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case SPEED_100:
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@ -2829,6 +2718,7 @@ static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
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if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
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switch (speed) {
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case SPEED_1000:
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case SPEED_2500:
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mcr |= PMCR_FORCE_EEE1G;
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break;
|
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case SPEED_100:
|
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@ -2840,63 +2730,6 @@ static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
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mt7530_set(priv, MT7530_PMCR_P(port), mcr);
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}
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|
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static int
|
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mt7531_cpu_port_config(struct dsa_switch *ds, int port)
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{
|
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struct mt7530_priv *priv = ds->priv;
|
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phy_interface_t interface;
|
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int speed;
|
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int ret;
|
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|
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switch (port) {
|
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case 5:
|
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if (!priv->p5_sgmii)
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interface = PHY_INTERFACE_MODE_RGMII;
|
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else
|
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interface = PHY_INTERFACE_MODE_2500BASEX;
|
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|
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priv->p5_interface = interface;
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break;
|
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case 6:
|
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interface = PHY_INTERFACE_MODE_2500BASEX;
|
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|
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priv->p6_interface = interface;
|
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break;
|
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default:
|
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return -EINVAL;
|
||||
}
|
||||
|
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
|
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speed = SPEED_2500;
|
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else
|
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speed = SPEED_1000;
|
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|
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ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
|
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if (ret)
|
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return ret;
|
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mt7530_write(priv, MT7530_PMCR_P(port),
|
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PMCR_CPU_PORT_SETTING(priv->id));
|
||||
mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
|
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speed, DUPLEX_FULL, true, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7988_cpu_port_config(struct dsa_switch *ds, int port)
|
||||
{
|
||||
struct mt7530_priv *priv = ds->priv;
|
||||
|
||||
mt7530_write(priv, MT7530_PMCR_P(port),
|
||||
PMCR_CPU_PORT_SETTING(priv->id));
|
||||
|
||||
mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
|
||||
PHY_INTERFACE_MODE_INTERNAL, NULL,
|
||||
SPEED_10000, DUPLEX_FULL, true, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
|
||||
struct phylink_config *config)
|
||||
{
|
||||
@ -2979,17 +2812,9 @@ static int
|
||||
mt753x_setup(struct dsa_switch *ds)
|
||||
{
|
||||
struct mt7530_priv *priv = ds->priv;
|
||||
int i, ret;
|
||||
int ret = priv->info->sw_setup(ds);
|
||||
int i;
|
||||
|
||||
/* Initialise the PCS devices */
|
||||
for (i = 0; i < priv->ds->num_ports; i++) {
|
||||
priv->pcs[i].pcs.ops = priv->info->pcs_ops;
|
||||
priv->pcs[i].pcs.neg_mode = true;
|
||||
priv->pcs[i].priv = priv;
|
||||
priv->pcs[i].port = i;
|
||||
}
|
||||
|
||||
ret = priv->info->sw_setup(ds);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -3001,6 +2826,14 @@ mt753x_setup(struct dsa_switch *ds)
|
||||
if (ret && priv->irq)
|
||||
mt7530_free_irq_common(priv);
|
||||
|
||||
/* Initialise the PCS devices */
|
||||
for (i = 0; i < priv->ds->num_ports; i++) {
|
||||
priv->pcs[i].pcs.ops = priv->info->pcs_ops;
|
||||
priv->pcs[i].pcs.neg_mode = true;
|
||||
priv->pcs[i].priv = priv;
|
||||
priv->pcs[i].port = i;
|
||||
}
|
||||
|
||||
if (priv->create_sgmii) {
|
||||
ret = priv->create_sgmii(priv);
|
||||
if (ret && priv->irq)
|
||||
@ -3155,7 +2988,6 @@ const struct mt753x_info mt753x_table[] = {
|
||||
.phy_write_c22 = mt7531_ind_c22_phy_write,
|
||||
.phy_read_c45 = mt7531_ind_c45_phy_read,
|
||||
.phy_write_c45 = mt7531_ind_c45_phy_write,
|
||||
.cpu_port_config = mt7531_cpu_port_config,
|
||||
.mac_port_get_caps = mt7531_mac_port_get_caps,
|
||||
.mac_port_config = mt7531_mac_config,
|
||||
},
|
||||
@ -3167,9 +2999,7 @@ const struct mt753x_info mt753x_table[] = {
|
||||
.phy_write_c22 = mt7531_ind_c22_phy_write,
|
||||
.phy_read_c45 = mt7531_ind_c45_phy_read,
|
||||
.phy_write_c45 = mt7531_ind_c45_phy_write,
|
||||
.cpu_port_config = mt7988_cpu_port_config,
|
||||
.mac_port_get_caps = mt7988_mac_port_get_caps,
|
||||
.mac_port_config = mt7988_mac_config,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(mt753x_table);
|
||||
@ -3197,8 +3027,7 @@ mt7530_probe_common(struct mt7530_priv *priv)
|
||||
* properly.
|
||||
*/
|
||||
if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
|
||||
!priv->info->phy_write_c22 || !priv->info->mac_port_get_caps ||
|
||||
!priv->info->mac_port_config)
|
||||
!priv->info->phy_write_c22 || !priv->info->mac_port_get_caps)
|
||||
return -EINVAL;
|
||||
|
||||
priv->id = priv->info->id;
|
||||
|
||||
@ -304,20 +304,11 @@ enum mt7530_vlan_port_acc_frm {
|
||||
MT7531_FORCE_DPX | \
|
||||
MT7531_FORCE_RX_FC | \
|
||||
MT7531_FORCE_TX_FC)
|
||||
#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
|
||||
MT7531_FORCE_MODE : PMCR_FORCE_MODE)
|
||||
#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
|
||||
PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
|
||||
PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
|
||||
PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
|
||||
PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
|
||||
#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
|
||||
PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
|
||||
PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
|
||||
PMCR_TX_EN | PMCR_RX_EN | \
|
||||
PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
|
||||
PMCR_FORCE_SPEED_1000 | \
|
||||
PMCR_FORCE_FDX | PMCR_FORCE_LNK)
|
||||
|
||||
#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
|
||||
#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
|
||||
@ -724,15 +715,14 @@ struct mt753x_info {
|
||||
int regnum);
|
||||
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
|
||||
int regnum, u16 val);
|
||||
int (*cpu_port_config)(struct dsa_switch *ds, int port);
|
||||
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
|
||||
struct phylink_config *config);
|
||||
void (*mac_port_validate)(struct dsa_switch *ds, int port,
|
||||
phy_interface_t interface,
|
||||
unsigned long *supported);
|
||||
int (*mac_port_config)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode,
|
||||
phy_interface_t interface);
|
||||
void (*mac_port_config)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode,
|
||||
phy_interface_t interface);
|
||||
};
|
||||
|
||||
/* struct mt7530_priv - This is the main data structure for holding the state
|
||||
@ -750,7 +740,6 @@ struct mt753x_info {
|
||||
* @ports: Holding the state among ports
|
||||
* @reg_mutex: The lock for protecting among process accessing
|
||||
* registers
|
||||
* @p6_interface Holding the current port 6 interface
|
||||
* @p5_intf_sel: Holding the current port 5 interface select
|
||||
* @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
|
||||
* has got SGMII
|
||||
@ -772,8 +761,6 @@ struct mt7530_priv {
|
||||
const struct mt753x_info *info;
|
||||
unsigned int id;
|
||||
bool mcm;
|
||||
phy_interface_t p6_interface;
|
||||
phy_interface_t p5_interface;
|
||||
enum p5_interface_select p5_intf_sel;
|
||||
bool p5_sgmii;
|
||||
u8 mirror_rx;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user