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powerpc: Use lwarx/ldarx directly instead of PPC_LWARX/LDARX macros
Force the eh flag at 0 on PPC32. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1fc81f07cabebb875b963e295408cc3dd38c8d85.1614674882.git.christophe.leroy@csgroup.eu
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@ -17,7 +17,7 @@
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#define PPC_LONG stringify_in_c(.8byte)
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#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
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#define PPC_TLNEI stringify_in_c(tdnei)
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#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
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#define PPC_LLARX stringify_in_c(ldarx)
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#define PPC_STLCX stringify_in_c(stdcx.)
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#define PPC_CNTLZL stringify_in_c(cntlzd)
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#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
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@ -50,7 +50,7 @@
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#define PPC_LONG stringify_in_c(.long)
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#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
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#define PPC_TLNEI stringify_in_c(twnei)
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#define PPC_LLARX(t, a, b, eh) PPC_LWARX(t, a, b, eh)
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#define PPC_LLARX stringify_in_c(lwarx)
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#define PPC_STLCX stringify_in_c(stwcx.)
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#define PPC_CNTLZL stringify_in_c(cntlzw)
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#define PPC_MTOCRF stringify_in_c(mtcrf)
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@ -207,7 +207,7 @@ arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)
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int r, o = *old;
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__asm__ __volatile__ (
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"1:\t" PPC_LWARX(%0,0,%2,1) " # atomic_try_cmpxchg_acquire \n"
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"1: lwarx %0,0,%2,%5 # atomic_try_cmpxchg_acquire \n"
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" cmpw 0,%0,%3 \n"
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" bne- 2f \n"
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" stwcx. %4,0,%2 \n"
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@ -215,7 +215,7 @@ arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)
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"\t" PPC_ACQUIRE_BARRIER " \n"
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"2: \n"
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: "=&r" (r), "+m" (v->counter)
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: "r" (&v->counter), "r" (o), "r" (new)
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: "r" (&v->counter), "r" (o), "r" (new), "i" (IS_ENABLED(CONFIG_PPC64) ? 1 : 0)
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: "cr0", "memory");
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if (unlikely(r != o))
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@ -70,7 +70,7 @@ static inline void fn(unsigned long mask, \
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unsigned long *p = (unsigned long *)_p; \
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__asm__ __volatile__ ( \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,0) "\n" \
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"1:" PPC_LLARX "%0,0,%3,0\n" \
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stringify_in_c(op) "%0,%0,%2\n" \
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PPC_STLCX "%0,0,%3\n" \
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"bne- 1b\n" \
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@ -115,13 +115,13 @@ static inline unsigned long fn( \
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unsigned long *p = (unsigned long *)_p; \
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__asm__ __volatile__ ( \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
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"1:" PPC_LLARX "%0,0,%3,%4\n" \
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stringify_in_c(op) "%1,%0,%2\n" \
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PPC_STLCX "%1,0,%3\n" \
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"bne- 1b\n" \
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postfix \
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: "=&r" (old), "=&r" (t) \
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: "r" (mask), "r" (p) \
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: "r" (mask), "r" (p), "i" (IS_ENABLED(CONFIG_PPC64) ? eh : 0) \
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: "cc", "memory"); \
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return (old & mask); \
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}
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@ -170,7 +170,7 @@ clear_bit_unlock_return_word(int nr, volatile unsigned long *addr)
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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"1:" PPC_LLARX(%0,0,%3,0) "\n"
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"1:" PPC_LLARX "%0,0,%3,0\n"
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"andc %1,%0,%2\n"
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PPC_STLCX "%1,0,%3\n"
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"bne- 1b\n"
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@ -576,8 +576,6 @@
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#define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
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#define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
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#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
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#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
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#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
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#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
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#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
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#define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
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@ -51,7 +51,7 @@ static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
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token = LOCK_TOKEN;
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__asm__ __volatile__(
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"1: " PPC_LWARX(%0,0,%2,1) "\n\
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"1: lwarx %0,0,%2,1\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n\
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stwcx. %1,0,%2\n\
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@ -179,7 +179,7 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw)
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long tmp;
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__asm__ __volatile__(
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"1: " PPC_LWARX(%0,0,%1,1) "\n"
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"1: lwarx %0,0,%1,1\n"
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__DO_SIGN_EXTEND
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" addic. %0,%0,1\n\
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ble- 2f\n"
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@ -203,7 +203,7 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw)
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token = WRLOCK_TOKEN;
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__asm__ __volatile__(
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"1: " PPC_LWARX(%0,0,%2,1) "\n\
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"1: lwarx %0,0,%2,1\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n"
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" stwcx. %1,0,%2\n\
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