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mtd: Workaround wrong write protect status on some xD cards
Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -434,6 +434,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
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static int nand_check_wp(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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/* broken xD cards report WP despite being writable */
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if (chip->options & NAND_BROKEN_XD)
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return 0;
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/* Check the WP bit */
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chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
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@ -3175,7 +3180,8 @@ int nand_scan_tail(struct mtd_info *mtd)
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/* Fill in remaining MTD driver data */
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mtd->type = MTD_NANDFLASH;
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mtd->flags = MTD_CAP_NANDFLASH;
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mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
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MTD_CAP_NANDFLASH;
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mtd->erase = nand_erase;
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mtd->point = NULL;
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mtd->unpoint = NULL;
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@ -182,6 +182,12 @@ typedef enum {
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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/* Device is one of 'new' xD cards that expose fake nand command set */
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#define NAND_BROKEN_XD 0x00000400
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/* Device behaves just like nand, but is readonly */
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#define NAND_ROM 0x00000800
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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