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clk: samsung: exynos7: add gate clock for ADC block

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Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Abhilash Kesavan 2014-10-28 16:48:55 +05:30 committed by Sylwester Nawrocki
parent 2ab2dfe5d4
commit 932e98224d
2 changed files with 4 additions and 1 deletions
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2
drivers/clk/samsung/clk-exynos7.c
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@ -486,6 +486,8 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 20, 0, 0),
GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 21, 0, 0),

3
include/dt-bindings/clock/exynos7-clk.h
View File

@ -55,7 +55,8 @@
#define PCLK_HSI2C11 9
#define PCLK_PWM 10
#define SCLK_PWM 11
#define PERIC0_NR_CLK 12
#define PCLK_ADCIF 12
#define PERIC0_NR_CLK 13
/* PERIC1 */
#define PCLK_UART1 1