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staging: comedi: plx9052: tidy up the register defines

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The PLX INTCSR register defines are a bit wordy and many of them
are not used anywhere.

For aesthetic reasons, remove all the *_MASK and *_DISABLED defines
and rename the remaining bit defines so they are not as wordy.

Convert all the bit defines to bit shifts.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2013-04-12 13:39:51 -07:00 committed by Greg Kroah-Hartman
parent 3646af9fda
commit 926848220e
3 changed files with 32 additions and 74 deletions
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36
drivers/staging/comedi/drivers/amplc_pc236.c
View File

@ -75,23 +75,19 @@ unused.
#define PC236_IO_SIZE 4
#define PC236_LCR_IO_SIZE 128
/*
* INTCSR values for PCI236.
*/
/* Disable interrupt, also clear any interrupt there */
#define PCI236_INTR_DISABLE (PLX9052_INTCSR_LI1ENAB_DISABLED \
| PLX9052_INTCSR_LI1POL_HIGH \
| PLX9052_INTCSR_LI2POL_HIGH \
| PLX9052_INTCSR_PCIENAB_DISABLED \
| PLX9052_INTCSR_LI1SEL_EDGE \
| PLX9052_INTCSR_LI1CLRINT_ASSERTED)
/* Enable interrupt, also clear any interrupt there. */
#define PCI236_INTR_ENABLE (PLX9052_INTCSR_LI1ENAB_ENABLED \
| PLX9052_INTCSR_LI1POL_HIGH \
| PLX9052_INTCSR_LI2POL_HIGH \
| PLX9052_INTCSR_PCIENAB_ENABLED \
| PLX9052_INTCSR_LI1SEL_EDGE \
| PLX9052_INTCSR_LI1CLRINT_ASSERTED)
/* Disable, and clear, interrupts */
#define PCI236_INTR_DISABLE (PLX9052_INTCSR_LI1POL | \
PLX9052_INTCSR_LI2POL | \
PLX9052_INTCSR_LI1SEL | \
PLX9052_INTCSR_LI1CLRINT)
/* Enable, and clear, interrupts */
#define PCI236_INTR_ENABLE (PLX9052_INTCSR_LI1ENAB | \
PLX9052_INTCSR_LI1POL | \
PLX9052_INTCSR_LI2POL | \
PLX9052_INTCSR_PCIENAB | \
PLX9052_INTCSR_LI1SEL | \
PLX9052_INTCSR_LI1CLRINT)
/*
* Board descriptions for Amplicon PC36AT and PCI236.
@ -257,14 +253,14 @@ static int pc236_intr_check(struct comedi_device *dev)
struct pc236_private *devpriv = dev->private;
int retval = 0;
unsigned long flags;
unsigned int intcsr;
spin_lock_irqsave(&dev->spinlock, flags);
if (devpriv->enable_irq) {
retval = 1;
if (is_pci_board(thisboard)) {
if ((inl(devpriv->lcr_iobase + PLX9052_INTCSR)
& PLX9052_INTCSR_LI1STAT_MASK)
== PLX9052_INTCSR_LI1STAT_INACTIVE) {
intcsr = inl(devpriv->lcr_iobase + PLX9052_INTCSR);
if (!(intcsr & PLX9052_INTCSR_LI1STAT)) {
retval = 0;
} else {
/* Clear interrupt and keep it enabled. */

1
drivers/staging/comedi/drivers/cb_pcimdas.c
View File

@ -46,6 +46,7 @@ See http://www.mccdaq.com/PDFs/Manuals/pcim-das1602-16.pdf for more details.
#include "../comedidev.h"
#include "plx9052.h"
#include "8255.h"
/* #define CBPCIMDAS_DEBUG */

69
drivers/staging/comedi/drivers/plx9052.h
View File

@ -27,60 +27,21 @@
#define _PLX9052_H_
/*
* PLX PCI9052 INTCSR register.
* INTCSR - Interrupt Control/Status register
*/
#define PLX9052_INTCSR 0x4C /* Offset in Local Configuration Registers */
/* Local Interrupt 1 Enable */
#define PLX9052_INTCSR_LI1ENAB_MASK 0x0001
#define PLX9052_INTCSR_LI1ENAB_DISABLED 0x0000
#define PLX9052_INTCSR_LI1ENAB_ENABLED 0x0001
/* Local Interrupt 1 Polarity */
#define PLX9052_INTCSR_LI1POL_MASK 0x0002
#define PLX9052_INTCSR_LI1POL_LOW 0x0000
#define PLX9052_INTCSR_LI1POL_HIGH 0x0002
/* Local Interrupt 1 Status (read-only) */
#define PLX9052_INTCSR_LI1STAT_MASK 0x0004
#define PLX9052_INTCSR_LI1STAT_INACTIVE 0x0000
#define PLX9052_INTCSR_LI1STAT_ACTIVE 0x0004
/* Local Interrupt 2 Enable */
#define PLX9052_INTCSR_LI2ENAB_MASK 0x0008
#define PLX9052_INTCSR_LI2ENAB_DISABLED 0x0000
#define PLX9052_INTCSR_LI2ENAB_ENABLED 0x0008
/* Local Interrupt 2 Polarity */
#define PLX9052_INTCSR_LI2POL_MASK 0x0010
#define PLX9052_INTCSR_LI2POL_LOW 0x0000
#define PLX9052_INTCSR_LI2POL_HIGH 0x0010
/* Local Interrupt 2 Status (read-only) */
#define PLX9052_INTCSR_LI2STAT_MASK 0x0020
#define PLX9052_INTCSR_LI2STAT_INACTIVE 0x0000
#define PLX9052_INTCSR_LI2STAT_ACTIVE 0x0020
/* PCI Interrupt Enable */
#define PLX9052_INTCSR_PCIENAB_MASK 0x0040
#define PLX9052_INTCSR_PCIENAB_DISABLED 0x0000
#define PLX9052_INTCSR_PCIENAB_ENABLED 0x0040
/* Software Interrupt */
#define PLX9052_INTCSR_SOFTINT_MASK 0x0080
#define PLX9052_INTCSR_SOFTINT_UNASSERTED 0x0000
#define PLX9052_INTCSR_SOFTINT_ASSERTED 0x0080
/* Local Interrupt 1 Select Enable */
#define PLX9052_INTCSR_LI1SEL_MASK 0x0100
#define PLX9052_INTCSR_LI1SEL_LEVEL 0x0000
#define PLX9052_INTCSR_LI1SEL_EDGE 0x0100
/* Local Interrupt 2 Select Enable */
#define PLX9052_INTCSR_LI2SEL_MASK 0x0200
#define PLX9052_INTCSR_LI2SEL_LEVEL 0x0000
#define PLX9052_INTCSR_LI2SEL_EDGE 0x0200
/* Local Edge Triggerable Interrupt 1 Clear Bit */
#define PLX9052_INTCSR_LI1CLRINT_MASK 0x0400
#define PLX9052_INTCSR_LI1CLRINT_UNASSERTED 0x0000
#define PLX9052_INTCSR_LI1CLRINT_ASSERTED 0x0400
/* Local Edge Triggerable Interrupt 2 Clear Bit */
#define PLX9052_INTCSR_LI2CLRINT_MASK 0x0800
#define PLX9052_INTCSR_LI2CLRINT_UNASSERTED 0x0000
#define PLX9052_INTCSR_LI2CLRINT_ASSERTED 0x0800
/* ISA Interface Mode Enable (read-only over PCI bus) */
#define PLX9052_INTCSR_ISAMODE_MASK 0x1000
#define PLX9052_INTCSR_ISAMODE_DISABLED 0x0000
#define PLX9052_INTCSR_ISAMODE_ENABLED 0x1000
#define PLX9052_INTCSR 0x4c
#define PLX9052_INTCSR_LI1ENAB (1 << 0) /* LI1 enabled */
#define PLX9052_INTCSR_LI1POL (1 << 1) /* LI1 active high */
#define PLX9052_INTCSR_LI1STAT (1 << 2) /* LI1 active */
#define PLX9052_INTCSR_LI2ENAB (1 << 3) /* LI2 enabled */
#define PLX9052_INTCSR_LI2POL (1 << 4) /* LI2 active high */
#define PLX9052_INTCSR_LI2STAT (1 << 5) /* LI2 active */
#define PLX9052_INTCSR_PCIENAB (1 << 6) /* PCIINT enabled */
#define PLX9052_INTCSR_SOFTINT (1 << 7) /* generate soft int */
#define PLX9052_INTCSR_LI1SEL (1 << 8) /* LI1 edge */
#define PLX9052_INTCSR_LI2SEL (1 << 9) /* LI2 edge */
#define PLX9052_INTCSR_LI1CLRINT (1 << 10) /* LI1 clear int */
#define PLX9052_INTCSR_LI2CLRINT (1 << 11) /* LI2 clear int */
#define PLX9052_INTCSR_ISAMODE (1 << 12) /* ISA interface mode */
#endif /* _PLX9052_H_ */