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pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Mesih Kilinc
Linus Walleij
parent
bbeb6a6ded
commit
9088276d1a
@ -6,6 +6,10 @@ config PINCTRL_SUNXI
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select GENERIC_PINCONF
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select GPIOLIB
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config PINCTRL_SUNIV_F1C100S
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def_bool MACH_SUNIV
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select PINCTRL_SUNXI
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config PINCTRL_SUN4I_A10
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def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
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select PINCTRL_SUNXI
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@ -3,6 +3,7 @@
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obj-y += pinctrl-sunxi.o
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# SoC Drivers
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obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o
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obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
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obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o
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obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
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416
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
Normal file
416
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
Normal file
@ -0,0 +1,416 @@
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/*
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* Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
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*
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* Copyright (C) 2018 Icenowy Zheng
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*
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* Icenowy Zheng <icenowy@aosc.io>
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*
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* Copyright (C) 2014 Jackie Hwang
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*
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* Jackie Hwang <huangshr@allwinnertech.com>
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*
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* Copyright (C) 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* Copyright (C) 2014 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
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SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
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SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
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SUNXI_FUNCTION(0x6, "spi1")), /* CS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
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SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
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SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
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SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
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SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
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SUNXI_FUNCTION(0x4, "i2s"), /* IN */
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SUNXI_FUNCTION(0x5, "uart1"), /* RX */
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SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
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SUNXI_FUNCTION(0x3, "ir0"), /* RX */
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SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
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SUNXI_FUNCTION(0x5, "uart1"), /* TX */
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SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
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SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
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SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
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SUNXI_FUNCTION(0x6, "spi1")), /* CS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
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SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
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SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
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SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "dram"), /* CKE */
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SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
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SUNXI_FUNCTION(0x4, "i2s"), /* IN */
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SUNXI_FUNCTION(0x5, "uart1"), /* RX */
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SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
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SUNXI_FUNCTION(0x3, "ir0"), /* RX */
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SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
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SUNXI_FUNCTION(0x5, "uart1"), /* TX */
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SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
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SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi0"), /* CS */
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SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
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SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
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SUNXI_FUNCTION(0x3, "uart0")), /* TX */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
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SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
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SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
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SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
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SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
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SUNXI_FUNCTION(0x3, "uart1"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
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SUNXI_FUNCTION(0x3, "uart1"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
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SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
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SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
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SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
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SUNXI_FUNCTION(0x3, "i2s"), /* IN */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
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SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
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SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
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SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
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SUNXI_FUNCTION(0x3, "uart2"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
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SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
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SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
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SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
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SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
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SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
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SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
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SUNXI_FUNCTION(0x3, "spi0"), /* CS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* DE */
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SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
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SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
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SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
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SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
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SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
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SUNXI_FUNCTION(0x5, "uart0"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
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SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
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SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
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SUNXI_FUNCTION(0x5, "uart0"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
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SUNXI_FUNCTION(0x4, "clk"), /* OUT */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D0 */
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SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
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SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
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SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D1 */
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SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
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SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
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SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
|
||||
SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
|
||||
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
|
||||
SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
|
||||
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
|
||||
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
|
||||
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
|
||||
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
|
||||
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
|
||||
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
|
||||
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
|
||||
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
|
||||
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
|
||||
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
|
||||
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
|
||||
SUNXI_FUNCTION(0x4, "ir"), /* RX */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
|
||||
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
|
||||
SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
|
||||
|
||||
/* Hole */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
|
||||
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
|
||||
SUNXI_FUNCTION(0x4, "ir0"), /* MS */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
|
||||
SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
|
||||
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
|
||||
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
|
||||
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
|
||||
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
|
||||
SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
|
||||
};
|
||||
|
||||
static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
|
||||
.pins = suniv_f1c100s_pins,
|
||||
.npins = ARRAY_SIZE(suniv_f1c100s_pins),
|
||||
.irq_banks = 3,
|
||||
};
|
||||
|
||||
static int suniv_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return sunxi_pinctrl_init(pdev,
|
||||
&suniv_f1c100s_pinctrl_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
|
||||
{ .compatible = "allwinner,suniv-f1c100s-pinctrl", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver suniv_f1c100s_pinctrl_driver = {
|
||||
.probe = suniv_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "suniv-f1c100s-pinctrl",
|
||||
.of_match_table = suniv_f1c100s_pinctrl_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
|
||||
Loading…
Reference in New Issue
Block a user