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ARM: shmobile: bockw: add SMSC support on reference

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This patch enables INTC IRQ, and SMSC IRQ.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Kuninori Morimoto 2013-10-02 01:33:36 -07:00 committed by Simon Horman
parent b6d5a1b1c3
commit 90357fcbf2
1 changed files with 20 additions and 0 deletions
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20
arch/arm/mach-shmobile/board-bockw-reference.c
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@ -36,15 +36,35 @@ static const struct pinctrl_map bockw_pinctrl_map[] = {
"scif0_ctrl", "scif0"), "scif0_ctrl", "scif0"),
}; };
#define FPGA 0x18200000
#define IRQ0MR 0x30
#define COMCTLR 0x101c
static void __init bockw_init(void) static void __init bockw_init(void)
{ {
static void __iomem *fpga;
r8a7778_clock_init(); r8a7778_clock_init();
r8a7778_init_irq_extpin_dt(1);
pinctrl_register_mappings(bockw_pinctrl_map, pinctrl_register_mappings(bockw_pinctrl_map,
ARRAY_SIZE(bockw_pinctrl_map)); ARRAY_SIZE(bockw_pinctrl_map));
r8a7778_pinmux_init(); r8a7778_pinmux_init();
r8a7778_add_dt_devices(); r8a7778_add_dt_devices();
fpga = ioremap_nocache(FPGA, SZ_1M);
if (fpga) {
/*
* CAUTION
*
* IRQ0/1 is cascaded interrupt from FPGA.
* it should be cared in the future
* Now, it is assuming IRQ0 was used only from SMSC.
*/
u16 val = ioread16(fpga + IRQ0MR);
val &= ~(1 << 4); /* enable SMSC911x */
iowrite16(val, fpga + IRQ0MR);
}
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
} }