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soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC

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Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the mode bitfield are different and the
0x0A value defined for the QMC mode is CPM1 specific.

In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-31-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This commit is contained in:
Herve Codina 2024-08-08 09:11:23 +02:00 committed by Christophe Leroy
parent 278d799caa
commit 8f55d06b4c
1 changed files with 2 additions and 2 deletions
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4
drivers/soc/fsl/qe/qmc.c
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@ -27,7 +27,7 @@
#define SCC_GSMRL_ENR BIT(5)
#define SCC_GSMRL_ENT BIT(4)
#define SCC_GSMRL_MODE_MASK GENMASK(3, 0)
#define SCC_GSMRL_MODE_QMC FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
#define SCC_CPM1_GSMRL_MODE_QMC FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
/* SCC general mode register low (32 bits) */
#define SCC_GSMRH 0x04
@ -1642,7 +1642,7 @@ static int qmc_cpm1_init_scc(struct qmc *qmc)
qmc_write32(qmc->scc_regs + SCC_GSMRH, val);
/* enable QMC mode */
qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_CPM1_GSMRL_MODE_QMC);
/* Disable and clear interrupts */
qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);