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dmaengine: Add hisilicon k3 DMA engine driver
Add dmaengine driver for hisilicon k3 platform based on virt_dma Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Kai Yang <jean.yangkai@huawei.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Zhangfei Gao
Vinod Koul
parent
0429936697
commit
8e6152bc66
46
Documentation/devicetree/bindings/dma/k3dma.txt
Normal file
46
Documentation/devicetree/bindings/dma/k3dma.txt
Normal file
@ -0,0 +1,46 @@
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* Hisilicon K3 DMA controller
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See dma.txt first
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Required properties:
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- compatible: Should be "hisilicon,k3-dma-1.0"
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain one interrupt shared by all channel
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- #dma-cells: see dma.txt, should be 1, para number
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- dma-channels: physical channels supported
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- dma-requests: virtual channels supported, each virtual channel
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have specific request line
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- clocks: clock required
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Example:
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Controller:
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dma0: dma@fcd02000 {
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compatible = "hisilicon,k3-dma-1.0";
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reg = <0xfcd02000 0x1000>;
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#dma-cells = <1>;
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dma-channels = <16>;
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dma-requests = <27>;
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interrupts = <0 12 4>;
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clocks = <&pclk>;
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status = "disable";
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};
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Client:
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Use specific request line passing from dmax
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For example, i2c0 read channel request line is 18, while write channel use 19
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i2c0: i2c@fcb08000 {
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compatible = "snps,designware-i2c";
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dmas = <&dma0 18 /* read channel */
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&dma0 19>; /* write channel */
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dma-names = "rx", "tx";
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};
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i2c1: i2c@fcb09000 {
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compatible = "snps,designware-i2c";
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dmas = <&dma0 20 /* read channel */
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&dma0 21>; /* write channel */
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dma-names = "rx", "tx";
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};
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@ -300,6 +300,15 @@ config DMA_JZ4740
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config K3_DMA
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tristate "Hisilicon K3 DMA support"
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depends on ARCH_HI3xxx
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the DMA engine for Hisilicon K3 platform
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devices.
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config DMA_ENGINE
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bool
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@ -39,3 +39,4 @@ obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
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obj-$(CONFIG_K3_DMA) += k3dma.o
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837
drivers/dma/k3dma.c
Normal file
837
drivers/dma/k3dma.c
Normal file
@ -0,0 +1,837 @@
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/*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2013 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/of_dma.h>
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#include "virt-dma.h"
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#define DRIVER_NAME "k3-dma"
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#define DMA_ALIGN 3
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#define DMA_MAX_SIZE 0x1ffc
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#define INT_STAT 0x00
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#define INT_TC1 0x04
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#define INT_ERR1 0x0c
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#define INT_ERR2 0x10
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#define INT_TC1_MASK 0x18
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#define INT_ERR1_MASK 0x20
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#define INT_ERR2_MASK 0x24
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#define INT_TC1_RAW 0x600
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#define INT_ERR1_RAW 0x608
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#define INT_ERR2_RAW 0x610
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#define CH_PRI 0x688
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#define CH_STAT 0x690
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#define CX_CUR_CNT 0x704
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#define CX_LLI 0x800
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#define CX_CNT 0x810
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#define CX_SRC 0x814
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#define CX_DST 0x818
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#define CX_CFG 0x81c
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#define AXI_CFG 0x820
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#define AXI_CFG_DEFAULT 0x201201
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#define CX_LLI_CHAIN_EN 0x2
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#define CX_CFG_EN 0x1
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#define CX_CFG_MEM2PER (0x1 << 2)
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#define CX_CFG_PER2MEM (0x2 << 2)
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#define CX_CFG_SRCINCR (0x1 << 31)
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#define CX_CFG_DSTINCR (0x1 << 30)
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struct k3_desc_hw {
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u32 lli;
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u32 reserved[3];
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u32 count;
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u32 saddr;
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u32 daddr;
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u32 config;
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} __aligned(32);
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struct k3_dma_desc_sw {
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struct virt_dma_desc vd;
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dma_addr_t desc_hw_lli;
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size_t desc_num;
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size_t size;
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struct k3_desc_hw desc_hw[0];
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};
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struct k3_dma_phy;
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struct k3_dma_chan {
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u32 ccfg;
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struct virt_dma_chan vc;
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struct k3_dma_phy *phy;
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struct list_head node;
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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enum dma_status status;
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};
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struct k3_dma_phy {
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u32 idx;
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void __iomem *base;
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struct k3_dma_chan *vchan;
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struct k3_dma_desc_sw *ds_run;
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struct k3_dma_desc_sw *ds_done;
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};
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struct k3_dma_dev {
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struct dma_device slave;
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void __iomem *base;
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struct tasklet_struct task;
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spinlock_t lock;
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struct list_head chan_pending;
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struct k3_dma_phy *phy;
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struct k3_dma_chan *chans;
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struct clk *clk;
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u32 dma_channels;
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u32 dma_requests;
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};
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#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
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static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct k3_dma_chan, vc.chan);
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}
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static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
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{
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u32 val = 0;
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if (on) {
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val = readl_relaxed(phy->base + CX_CFG);
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val |= CX_CFG_EN;
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writel_relaxed(val, phy->base + CX_CFG);
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} else {
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val = readl_relaxed(phy->base + CX_CFG);
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val &= ~CX_CFG_EN;
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writel_relaxed(val, phy->base + CX_CFG);
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}
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}
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static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
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{
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u32 val = 0;
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k3_dma_pause_dma(phy, false);
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val = 0x1 << phy->idx;
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writel_relaxed(val, d->base + INT_TC1_RAW);
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writel_relaxed(val, d->base + INT_ERR1_RAW);
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writel_relaxed(val, d->base + INT_ERR2_RAW);
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}
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static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
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{
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writel_relaxed(hw->lli, phy->base + CX_LLI);
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writel_relaxed(hw->count, phy->base + CX_CNT);
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writel_relaxed(hw->saddr, phy->base + CX_SRC);
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writel_relaxed(hw->daddr, phy->base + CX_DST);
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writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
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writel_relaxed(hw->config, phy->base + CX_CFG);
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}
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static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
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{
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u32 cnt = 0;
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cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
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cnt &= 0xffff;
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return cnt;
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}
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static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
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{
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return readl_relaxed(phy->base + CX_LLI);
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}
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static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
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{
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return readl_relaxed(d->base + CH_STAT);
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}
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static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
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{
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if (on) {
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/* set same priority */
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writel_relaxed(0x0, d->base + CH_PRI);
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/* unmask irq */
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writel_relaxed(0xffff, d->base + INT_TC1_MASK);
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writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
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writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
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} else {
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/* mask irq */
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writel_relaxed(0x0, d->base + INT_TC1_MASK);
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writel_relaxed(0x0, d->base + INT_ERR1_MASK);
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writel_relaxed(0x0, d->base + INT_ERR2_MASK);
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}
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}
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static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
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{
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struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
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struct k3_dma_phy *p;
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struct k3_dma_chan *c;
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u32 stat = readl_relaxed(d->base + INT_STAT);
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u32 tc1 = readl_relaxed(d->base + INT_TC1);
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u32 err1 = readl_relaxed(d->base + INT_ERR1);
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u32 err2 = readl_relaxed(d->base + INT_ERR2);
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u32 i, irq_chan = 0;
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while (stat) {
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i = __ffs(stat);
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stat &= (stat - 1);
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if (likely(tc1 & BIT(i))) {
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p = &d->phy[i];
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c = p->vchan;
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if (c) {
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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vchan_cookie_complete(&p->ds_run->vd);
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p->ds_done = p->ds_run;
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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irq_chan |= BIT(i);
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}
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if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
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dev_warn(d->slave.dev, "DMA ERR\n");
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}
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writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
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writel_relaxed(err1, d->base + INT_ERR1_RAW);
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writel_relaxed(err2, d->base + INT_ERR2_RAW);
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if (irq_chan) {
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tasklet_schedule(&d->task);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static int k3_dma_start_txd(struct k3_dma_chan *c)
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{
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struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
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struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
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if (!c->phy)
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return -EAGAIN;
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if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
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return -EAGAIN;
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if (vd) {
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struct k3_dma_desc_sw *ds =
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container_of(vd, struct k3_dma_desc_sw, vd);
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/*
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* fetch and remove request from vc->desc_issued
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* so vc->desc_issued only contains desc pending
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*/
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list_del(&ds->vd.node);
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c->phy->ds_run = ds;
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c->phy->ds_done = NULL;
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/* start dma */
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k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
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return 0;
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}
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c->phy->ds_done = NULL;
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c->phy->ds_run = NULL;
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return -EAGAIN;
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}
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static void k3_dma_tasklet(unsigned long arg)
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{
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struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
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struct k3_dma_phy *p;
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struct k3_dma_chan *c, *cn;
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unsigned pch, pch_alloc = 0;
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/* check new dma request of running channel in vc->desc_issued */
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list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
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spin_lock_irq(&c->vc.lock);
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p = c->phy;
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if (p && p->ds_done) {
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if (k3_dma_start_txd(c)) {
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/* No current txd associated with this channel */
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dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
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/* Mark this channel free */
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c->phy = NULL;
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p->vchan = NULL;
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}
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}
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spin_unlock_irq(&c->vc.lock);
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}
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/* check new channel request in d->chan_pending */
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spin_lock_irq(&d->lock);
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for (pch = 0; pch < d->dma_channels; pch++) {
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p = &d->phy[pch];
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if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
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c = list_first_entry(&d->chan_pending,
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struct k3_dma_chan, node);
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/* remove from d->chan_pending */
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list_del_init(&c->node);
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pch_alloc |= 1 << pch;
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/* Mark this channel allocated */
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p->vchan = c;
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c->phy = p;
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dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
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}
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}
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spin_unlock_irq(&d->lock);
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for (pch = 0; pch < d->dma_channels; pch++) {
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if (pch_alloc & (1 << pch)) {
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p = &d->phy[pch];
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c = p->vchan;
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if (c) {
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spin_lock_irq(&c->vc.lock);
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k3_dma_start_txd(c);
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spin_unlock_irq(&c->vc.lock);
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}
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}
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}
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}
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static int k3_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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return 0;
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}
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static void k3_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_dev *d = to_k3_dma(chan->device);
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unsigned long flags;
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spin_lock_irqsave(&d->lock, flags);
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list_del_init(&c->node);
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spin_unlock_irqrestore(&d->lock, flags);
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vchan_free_chan_resources(&c->vc);
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c->ccfg = 0;
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}
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static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *state)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_dev *d = to_k3_dma(chan->device);
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struct k3_dma_phy *p;
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struct virt_dma_desc *vd;
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unsigned long flags;
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enum dma_status ret;
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size_t bytes = 0;
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ret = dma_cookie_status(&c->vc.chan, cookie, state);
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if (ret == DMA_SUCCESS)
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return ret;
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spin_lock_irqsave(&c->vc.lock, flags);
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p = c->phy;
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ret = c->status;
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/*
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* If the cookie is on our issue queue, then the residue is
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* its total size.
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*/
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vd = vchan_find_desc(&c->vc, cookie);
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if (vd) {
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bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
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} else if ((!p) || (!p->ds_run)) {
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bytes = 0;
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} else {
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struct k3_dma_desc_sw *ds = p->ds_run;
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u32 clli = 0, index = 0;
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bytes = k3_dma_get_curr_cnt(d, p);
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clli = k3_dma_get_curr_lli(p);
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index = (clli - ds->desc_hw_lli) / sizeof(struct k3_desc_hw);
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for (; index < ds->desc_num; index++) {
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bytes += ds->desc_hw[index].count;
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/* end of lli */
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if (!ds->desc_hw[index].lli)
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break;
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}
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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dma_set_residue(state, bytes);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void k3_dma_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
/* add request to vc->desc_issued */
|
||||
if (vchan_issue_pending(&c->vc)) {
|
||||
spin_lock(&d->lock);
|
||||
if (!c->phy) {
|
||||
if (list_empty(&c->node)) {
|
||||
/* if new channel, add chan_pending */
|
||||
list_add_tail(&c->node, &d->chan_pending);
|
||||
/* check in tasklet */
|
||||
tasklet_schedule(&d->task);
|
||||
dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
|
||||
}
|
||||
}
|
||||
spin_unlock(&d->lock);
|
||||
} else
|
||||
dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
}
|
||||
|
||||
static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
|
||||
dma_addr_t src, size_t len, u32 num, u32 ccfg)
|
||||
{
|
||||
if ((num + 1) < ds->desc_num)
|
||||
ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
|
||||
sizeof(struct k3_desc_hw);
|
||||
ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
|
||||
ds->desc_hw[num].count = len;
|
||||
ds->desc_hw[num].saddr = src;
|
||||
ds->desc_hw[num].daddr = dst;
|
||||
ds->desc_hw[num].config = ccfg;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
|
||||
struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
|
||||
size_t len, unsigned long flags)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_desc_sw *ds;
|
||||
size_t copy = 0;
|
||||
int num = 0;
|
||||
|
||||
if (!len)
|
||||
return NULL;
|
||||
|
||||
num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
|
||||
ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
|
||||
if (!ds) {
|
||||
dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
|
||||
return NULL;
|
||||
}
|
||||
ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
|
||||
ds->size = len;
|
||||
ds->desc_num = num;
|
||||
num = 0;
|
||||
|
||||
if (!c->ccfg) {
|
||||
/* default is memtomem, without calling device_control */
|
||||
c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
|
||||
c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
|
||||
c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
|
||||
}
|
||||
|
||||
do {
|
||||
copy = min_t(size_t, len, DMA_MAX_SIZE);
|
||||
k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
|
||||
|
||||
if (c->dir == DMA_MEM_TO_DEV) {
|
||||
src += copy;
|
||||
} else if (c->dir == DMA_DEV_TO_MEM) {
|
||||
dst += copy;
|
||||
} else {
|
||||
src += copy;
|
||||
dst += copy;
|
||||
}
|
||||
len -= copy;
|
||||
} while (len);
|
||||
|
||||
ds->desc_hw[num-1].lli = 0; /* end of link */
|
||||
return vchan_tx_prep(&c->vc, &ds->vd, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
|
||||
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
|
||||
enum dma_transfer_direction dir, unsigned long flags, void *context)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_desc_sw *ds;
|
||||
size_t len, avail, total = 0;
|
||||
struct scatterlist *sg;
|
||||
dma_addr_t addr, src = 0, dst = 0;
|
||||
int num = sglen, i;
|
||||
|
||||
if (sgl == 0)
|
||||
return NULL;
|
||||
|
||||
for_each_sg(sgl, sg, sglen, i) {
|
||||
avail = sg_dma_len(sg);
|
||||
if (avail > DMA_MAX_SIZE)
|
||||
num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
|
||||
}
|
||||
|
||||
ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
|
||||
if (!ds) {
|
||||
dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
|
||||
return NULL;
|
||||
}
|
||||
ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
|
||||
ds->desc_num = num;
|
||||
num = 0;
|
||||
|
||||
for_each_sg(sgl, sg, sglen, i) {
|
||||
addr = sg_dma_address(sg);
|
||||
avail = sg_dma_len(sg);
|
||||
total += avail;
|
||||
|
||||
do {
|
||||
len = min_t(size_t, avail, DMA_MAX_SIZE);
|
||||
|
||||
if (dir == DMA_MEM_TO_DEV) {
|
||||
src = addr;
|
||||
dst = c->dev_addr;
|
||||
} else if (dir == DMA_DEV_TO_MEM) {
|
||||
src = c->dev_addr;
|
||||
dst = addr;
|
||||
}
|
||||
|
||||
k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
|
||||
|
||||
addr += len;
|
||||
avail -= len;
|
||||
} while (avail);
|
||||
}
|
||||
|
||||
ds->desc_hw[num-1].lli = 0; /* end of link */
|
||||
ds->size = total;
|
||||
return vchan_tx_prep(&c->vc, &ds->vd, flags);
|
||||
}
|
||||
|
||||
static int k3_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
struct k3_dma_dev *d = to_k3_dma(chan->device);
|
||||
struct dma_slave_config *cfg = (void *)arg;
|
||||
struct k3_dma_phy *p = c->phy;
|
||||
unsigned long flags;
|
||||
u32 maxburst = 0, val = 0;
|
||||
enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
||||
LIST_HEAD(head);
|
||||
|
||||
switch (cmd) {
|
||||
case DMA_SLAVE_CONFIG:
|
||||
if (cfg == NULL)
|
||||
return -EINVAL;
|
||||
c->dir = cfg->direction;
|
||||
if (c->dir == DMA_DEV_TO_MEM) {
|
||||
c->ccfg = CX_CFG_DSTINCR;
|
||||
c->dev_addr = cfg->src_addr;
|
||||
maxburst = cfg->src_maxburst;
|
||||
width = cfg->src_addr_width;
|
||||
} else if (c->dir == DMA_MEM_TO_DEV) {
|
||||
c->ccfg = CX_CFG_SRCINCR;
|
||||
c->dev_addr = cfg->dst_addr;
|
||||
maxburst = cfg->dst_maxburst;
|
||||
width = cfg->dst_addr_width;
|
||||
}
|
||||
switch (width) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
||||
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
||||
case DMA_SLAVE_BUSWIDTH_8_BYTES:
|
||||
val = __ffs(width);
|
||||
break;
|
||||
default:
|
||||
val = 3;
|
||||
break;
|
||||
}
|
||||
c->ccfg |= (val << 12) | (val << 16);
|
||||
|
||||
if ((maxburst == 0) || (maxburst > 16))
|
||||
val = 16;
|
||||
else
|
||||
val = maxburst - 1;
|
||||
c->ccfg |= (val << 20) | (val << 24);
|
||||
c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
|
||||
|
||||
/* specific request line */
|
||||
c->ccfg |= c->vc.chan.chan_id << 4;
|
||||
break;
|
||||
|
||||
case DMA_TERMINATE_ALL:
|
||||
dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
|
||||
|
||||
/* Prevent this channel being scheduled */
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
|
||||
/* Clear the tx descriptor lists */
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
vchan_get_all_descriptors(&c->vc, &head);
|
||||
if (p) {
|
||||
/* vchan is assigned to a pchan - stop the channel */
|
||||
k3_dma_terminate_chan(p, d);
|
||||
c->phy = NULL;
|
||||
p->vchan = NULL;
|
||||
p->ds_run = p->ds_done = NULL;
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&c->vc, &head);
|
||||
break;
|
||||
|
||||
case DMA_PAUSE:
|
||||
dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
|
||||
if (c->status == DMA_IN_PROGRESS) {
|
||||
c->status = DMA_PAUSED;
|
||||
if (p) {
|
||||
k3_dma_pause_dma(p, false);
|
||||
} else {
|
||||
spin_lock(&d->lock);
|
||||
list_del_init(&c->node);
|
||||
spin_unlock(&d->lock);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_RESUME:
|
||||
dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
if (c->status == DMA_PAUSED) {
|
||||
c->status = DMA_IN_PROGRESS;
|
||||
if (p) {
|
||||
k3_dma_pause_dma(p, true);
|
||||
} else if (!list_empty(&c->vc.desc_issued)) {
|
||||
spin_lock(&d->lock);
|
||||
list_add_tail(&c->node, &d->chan_pending);
|
||||
spin_unlock(&d->lock);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
break;
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k3_dma_free_desc(struct virt_dma_desc *vd)
|
||||
{
|
||||
struct k3_dma_desc_sw *ds =
|
||||
container_of(vd, struct k3_dma_desc_sw, vd);
|
||||
|
||||
kfree(ds);
|
||||
}
|
||||
|
||||
static struct of_device_id k3_pdma_dt_ids[] = {
|
||||
{ .compatible = "hisilicon,k3-dma-1.0", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
|
||||
|
||||
static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct k3_dma_dev *d = ofdma->of_dma_data;
|
||||
unsigned int request = dma_spec->args[0];
|
||||
|
||||
if (request > d->dma_requests)
|
||||
return NULL;
|
||||
|
||||
return dma_get_slave_channel(&(d->chans[request].vc.chan));
|
||||
}
|
||||
|
||||
static int k3_dma_probe(struct platform_device *op)
|
||||
{
|
||||
struct k3_dma_dev *d;
|
||||
const struct of_device_id *of_id;
|
||||
struct resource *iores;
|
||||
int i, ret, irq = 0;
|
||||
|
||||
iores = platform_get_resource(op, IORESOURCE_MEM, 0);
|
||||
if (!iores)
|
||||
return -EINVAL;
|
||||
|
||||
d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d->base = devm_request_and_ioremap(&op->dev, iores);
|
||||
if (!d->base)
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
|
||||
if (of_id) {
|
||||
of_property_read_u32((&op->dev)->of_node,
|
||||
"dma-channels", &d->dma_channels);
|
||||
of_property_read_u32((&op->dev)->of_node,
|
||||
"dma-requests", &d->dma_requests);
|
||||
}
|
||||
|
||||
d->clk = devm_clk_get(&op->dev, NULL);
|
||||
if (IS_ERR(d->clk)) {
|
||||
dev_err(&op->dev, "no dma clk\n");
|
||||
return PTR_ERR(d->clk);
|
||||
}
|
||||
|
||||
irq = platform_get_irq(op, 0);
|
||||
ret = devm_request_irq(&op->dev, irq,
|
||||
k3_dma_int_handler, IRQF_DISABLED, DRIVER_NAME, d);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* init phy channel */
|
||||
d->phy = devm_kzalloc(&op->dev,
|
||||
d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL);
|
||||
if (d->phy == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < d->dma_channels; i++) {
|
||||
struct k3_dma_phy *p = &d->phy[i];
|
||||
|
||||
p->idx = i;
|
||||
p->base = d->base + i * 0x40;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&d->slave.channels);
|
||||
dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
|
||||
dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
|
||||
d->slave.dev = &op->dev;
|
||||
d->slave.device_alloc_chan_resources = k3_dma_alloc_chan_resources;
|
||||
d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
|
||||
d->slave.device_tx_status = k3_dma_tx_status;
|
||||
d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
|
||||
d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
|
||||
d->slave.device_issue_pending = k3_dma_issue_pending;
|
||||
d->slave.device_control = k3_dma_control;
|
||||
d->slave.copy_align = DMA_ALIGN;
|
||||
d->slave.chancnt = d->dma_requests;
|
||||
|
||||
/* init virtual channel */
|
||||
d->chans = devm_kzalloc(&op->dev,
|
||||
d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL);
|
||||
if (d->chans == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < d->dma_requests; i++) {
|
||||
struct k3_dma_chan *c = &d->chans[i];
|
||||
|
||||
c->status = DMA_IN_PROGRESS;
|
||||
INIT_LIST_HEAD(&c->node);
|
||||
c->vc.desc_free = k3_dma_free_desc;
|
||||
vchan_init(&c->vc, &d->slave);
|
||||
}
|
||||
|
||||
/* Enable clock before accessing registers */
|
||||
ret = clk_prepare_enable(d->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
k3_dma_enable_dma(d, true);
|
||||
|
||||
ret = dma_async_device_register(&d->slave);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_dma_controller_register((&op->dev)->of_node,
|
||||
k3_of_dma_simple_xlate, d);
|
||||
if (ret)
|
||||
goto of_dma_register_fail;
|
||||
|
||||
spin_lock_init(&d->lock);
|
||||
INIT_LIST_HEAD(&d->chan_pending);
|
||||
tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
|
||||
platform_set_drvdata(op, d);
|
||||
dev_info(&op->dev, "initialized\n");
|
||||
|
||||
return 0;
|
||||
|
||||
of_dma_register_fail:
|
||||
dma_async_device_unregister(&d->slave);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int k3_dma_remove(struct platform_device *op)
|
||||
{
|
||||
struct k3_dma_chan *c, *cn;
|
||||
struct k3_dma_dev *d = platform_get_drvdata(op);
|
||||
|
||||
dma_async_device_unregister(&d->slave);
|
||||
of_dma_controller_free((&op->dev)->of_node);
|
||||
|
||||
list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
|
||||
list_del(&c->vc.chan.device_node);
|
||||
tasklet_kill(&c->vc.task);
|
||||
}
|
||||
tasklet_kill(&d->task);
|
||||
clk_disable_unprepare(d->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k3_dma_suspend(struct device *dev)
|
||||
{
|
||||
struct k3_dma_dev *d = dev_get_drvdata(dev);
|
||||
u32 stat = 0;
|
||||
|
||||
stat = k3_dma_get_chan_stat(d);
|
||||
if (stat) {
|
||||
dev_warn(d->slave.dev,
|
||||
"chan %d is running fail to suspend\n", stat);
|
||||
return -1;
|
||||
}
|
||||
k3_dma_enable_dma(d, false);
|
||||
clk_disable_unprepare(d->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k3_dma_resume(struct device *dev)
|
||||
{
|
||||
struct k3_dma_dev *d = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(d->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
k3_dma_enable_dma(d, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend, k3_dma_resume);
|
||||
|
||||
static struct platform_driver k3_pdma_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &k3_dma_pmops,
|
||||
.of_match_table = k3_pdma_dt_ids,
|
||||
},
|
||||
.probe = k3_dma_probe,
|
||||
.remove = k3_dma_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(k3_pdma_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
|
||||
MODULE_ALIAS("platform:k3dma");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user