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libata: pata_pdc2027x PLL input clock fix

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Recently the PLL input clock of pata_pdc2027x is sometimes detected
higer than expected (e.g. 20.027 MHz compared to 16.714 MHz).
It seems sometimes the mdelay() function is not as precise as it
used to be. Per Alan's advice, HT or power management might affect
the precision of mdelay().

This patch calls gettimeofday() to mesure the time elapsed and
calculate the PLL input clock accordingly.

Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Albert Lee 2007-06-26 13:43:15 +08:00 committed by Jeff Garzik
parent abcdceb9d0
commit 8c781bf77a
1 changed files with 9 additions and 2 deletions
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11
drivers/ata/pata_pdc2027x.c
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@ -689,10 +689,12 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
u32 scr;
long start_count, end_count;
long pll_clock;
struct timeval start_time, end_time;
long pll_clock, usec_elapsed;
/* Read current counter value */
start_count = pdc_read_counter(host);
do_gettimeofday(&start_time);
/* Start the test mode */
scr = readl(mmio_base + PDC_SYS_CTL);
@ -705,6 +707,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
/* Read the counter values again */
end_count = pdc_read_counter(host);
do_gettimeofday(&end_time);
/* Stop the test mode */
scr = readl(mmio_base + PDC_SYS_CTL);
@ -713,7 +716,11 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
readl(mmio_base + PDC_SYS_CTL); /* flush */
/* calculate the input clock in Hz */
pll_clock = (start_count - end_count) * 10;
usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
(end_time.tv_usec - start_time.tv_usec);
pll_clock = (start_count - end_count) / 100 *
(100000000 / usec_elapsed);
PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);