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RDMA/mlx5: Add support in steering default miss
User can configure default miss rule in order to skip matching in the user domain and forward the packet to the kernel steering domain. When user requests a default miss rule, we add steering rule to forward the traffic to the next namespace. Link: https://lore.kernel.org/r/20200504053012.270689-5-leon@kernel.org Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Zhang <markz@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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@ -69,19 +69,32 @@ static const struct uverbs_attr_spec mlx5_ib_flow_type[] = {
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static int get_dests(struct uverbs_attr_bundle *attrs,
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static int get_dests(struct uverbs_attr_bundle *attrs,
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struct mlx5_ib_flow_matcher *fs_matcher, int *dest_id,
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struct mlx5_ib_flow_matcher *fs_matcher, int *dest_id,
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int *dest_type, struct ib_qp **qp)
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int *dest_type, struct ib_qp **qp, bool *def_miss)
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{
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{
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bool dest_devx, dest_qp;
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bool dest_devx, dest_qp;
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void *devx_obj;
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void *devx_obj;
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u32 flags;
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int err;
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dest_devx = uverbs_attr_is_valid(attrs,
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dest_devx = uverbs_attr_is_valid(attrs,
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MLX5_IB_ATTR_CREATE_FLOW_DEST_DEVX);
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MLX5_IB_ATTR_CREATE_FLOW_DEST_DEVX);
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dest_qp = uverbs_attr_is_valid(attrs,
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dest_qp = uverbs_attr_is_valid(attrs,
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MLX5_IB_ATTR_CREATE_FLOW_DEST_QP);
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MLX5_IB_ATTR_CREATE_FLOW_DEST_QP);
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if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS &&
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*def_miss = false;
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((dest_devx && dest_qp) || (!dest_devx && !dest_qp)))
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err = uverbs_get_flags32(&flags, attrs,
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return -EINVAL;
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MLX5_IB_ATTR_CREATE_FLOW_FLAGS,
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MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS);
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if (err)
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return err;
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*def_miss = flags & MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS;
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if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
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if (dest_devx && (dest_qp || *def_miss))
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return -EINVAL;
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else if (dest_qp && *def_miss)
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return -EINVAL;
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}
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/* Allow only DEVX object as dest when inserting to FDB */
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/* Allow only DEVX object as dest when inserting to FDB */
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if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB && !dest_devx)
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if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB && !dest_devx)
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@ -153,6 +166,7 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_CREATE_FLOW)(
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void *devx_obj, *cmd_in;
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void *devx_obj, *cmd_in;
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struct ib_uobject *uobj;
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struct ib_uobject *uobj;
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struct mlx5_ib_dev *dev;
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struct mlx5_ib_dev *dev;
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bool def_miss;
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if (!capable(CAP_NET_RAW))
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if (!capable(CAP_NET_RAW))
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return -EPERM;
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return -EPERM;
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@ -162,9 +176,12 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_CREATE_FLOW)(
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uobj = uverbs_attr_get_uobject(attrs, MLX5_IB_ATTR_CREATE_FLOW_HANDLE);
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uobj = uverbs_attr_get_uobject(attrs, MLX5_IB_ATTR_CREATE_FLOW_HANDLE);
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dev = mlx5_udata_to_mdev(&attrs->driver_udata);
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dev = mlx5_udata_to_mdev(&attrs->driver_udata);
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if (get_dests(attrs, fs_matcher, &dest_id, &dest_type, &qp))
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if (get_dests(attrs, fs_matcher, &dest_id, &dest_type, &qp, &def_miss))
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return -EINVAL;
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return -EINVAL;
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if (def_miss)
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flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS;
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len = uverbs_attr_get_uobjs_arr(attrs,
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len = uverbs_attr_get_uobjs_arr(attrs,
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX, &arr_flow_actions);
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX, &arr_flow_actions);
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if (len) {
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if (len) {
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@ -636,7 +653,10 @@ DECLARE_UVERBS_NAMED_METHOD(
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UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET,
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UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET,
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UVERBS_ATTR_MIN_SIZE(sizeof(u32)),
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UVERBS_ATTR_MIN_SIZE(sizeof(u32)),
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UA_OPTIONAL,
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UA_OPTIONAL,
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UA_ALLOC_AND_COPY));
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UA_ALLOC_AND_COPY),
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UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_FLAGS,
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enum mlx5_ib_create_flow_flags,
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UA_OPTIONAL));
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DECLARE_UVERBS_NAMED_METHOD_DESTROY(
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DECLARE_UVERBS_NAMED_METHOD_DESTROY(
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MLX5_IB_METHOD_DESTROY_FLOW,
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MLX5_IB_METHOD_DESTROY_FLOW,
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@ -4200,18 +4200,17 @@ mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
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if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
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if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
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dst[dst_num].type = dest_type;
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dst[dst_num].type = dest_type;
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dst[dst_num].tir_num = dest_id;
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dst[dst_num++].tir_num = dest_id;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
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} else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
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} else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
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dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
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dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
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dst[dst_num].ft_num = dest_id;
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dst[dst_num++].ft_num = dest_id;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
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} else {
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} else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_PORT) {
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dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
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dst[dst_num++].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
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flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
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}
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}
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dst_num++;
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if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
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if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
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dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
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dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
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@ -241,6 +241,10 @@ enum mlx5_ib_flow_type {
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MLX5_IB_FLOW_TYPE_MC_DEFAULT,
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MLX5_IB_FLOW_TYPE_MC_DEFAULT,
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};
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};
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enum mlx5_ib_create_flow_flags {
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MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS = 1 << 0,
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};
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enum mlx5_ib_create_flow_attrs {
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enum mlx5_ib_create_flow_attrs {
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MLX5_IB_ATTR_CREATE_FLOW_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_ATTR_CREATE_FLOW_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
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MLX5_IB_ATTR_CREATE_FLOW_MATCH_VALUE,
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MLX5_IB_ATTR_CREATE_FLOW_MATCH_VALUE,
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@ -251,6 +255,7 @@ enum mlx5_ib_create_flow_attrs {
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MLX5_IB_ATTR_CREATE_FLOW_TAG,
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MLX5_IB_ATTR_CREATE_FLOW_TAG,
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX,
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX,
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET,
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MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET,
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MLX5_IB_ATTR_CREATE_FLOW_FLAGS,
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};
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};
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enum mlx5_ib_destoy_flow_attrs {
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enum mlx5_ib_destoy_flow_attrs {
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