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crypto: hisilicon/qm - add queue isolation support for Kunpeng930
Kunpeng930 supports doorbell isolation to ensure that each queue has an independent doorbell address space. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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parent
6250383a20
commit
8bbecfb402
@ -97,6 +97,7 @@
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#define QM_QUE_ISO_EN 0x100154
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#define QM_CAPBILITY 0x100158
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#define QM_QP_NUN_MASK GENMASK(10, 0)
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#define QM_QP_DB_INTERVAL 0x10000
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#define QM_QP_MAX_NUM_SHIFT 11
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#define QM_DB_CMD_SHIFT_V2 12
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#define QM_DB_RAND_SHIFT_V2 16
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@ -186,6 +187,7 @@
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#define QM_CACHE_WB_DONE 0x208
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#define PCI_BAR_2 2
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#define PCI_BAR_4 4
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#define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
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#define QMC_ALIGN(sz) ALIGN(sz, 32)
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@ -571,21 +573,22 @@ static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
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static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
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{
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u64 doorbell;
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u64 dbase;
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void __iomem *io_base = qm->io_base;
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u16 randata = 0;
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u64 doorbell;
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if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
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dbase = QM_DOORBELL_SQ_CQ_BASE_V2;
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io_base = qm->db_io_base + (u64)qn * qm->db_interval +
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QM_DOORBELL_SQ_CQ_BASE_V2;
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else
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dbase = QM_DOORBELL_EQ_AEQ_BASE_V2;
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io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
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doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
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((u64)randata << QM_DB_RAND_SHIFT_V2) |
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((u64)index << QM_DB_INDEX_SHIFT_V2) |
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((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
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writeq(doorbell, qm->io_base + dbase);
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writeq(doorbell, io_base);
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}
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static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
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@ -2201,6 +2204,8 @@ static int hisi_qm_uacce_mmap(struct uacce_queue *q,
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{
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struct hisi_qp *qp = q->priv;
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struct hisi_qm *qm = qp->qm;
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resource_size_t phys_base = qm->db_phys_base +
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qp->qp_id * qm->db_interval;
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size_t sz = vma->vm_end - vma->vm_start;
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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@ -2212,16 +2217,19 @@ static int hisi_qm_uacce_mmap(struct uacce_queue *q,
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if (qm->ver == QM_HW_V1) {
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if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
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return -EINVAL;
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} else {
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} else if (qm->ver == QM_HW_V2 || !qm->use_db_isolation) {
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if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
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QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
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return -EINVAL;
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} else {
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if (sz > qm->db_interval)
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return -EINVAL;
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}
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vma->vm_flags |= VM_IO;
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return remap_pfn_range(vma, vma->vm_start,
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qm->phys_base >> PAGE_SHIFT,
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phys_base >> PAGE_SHIFT,
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sz, pgprot_noncached(vma->vm_page_prot));
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case UACCE_QFRT_DUS:
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if (sz != qp->qdma.size)
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@ -2336,14 +2344,20 @@ static int qm_alloc_uacce(struct hisi_qm *qm)
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uacce->priv = qm;
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uacce->algs = qm->algs;
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if (qm->ver == QM_HW_V1) {
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mmio_page_nr = QM_DOORBELL_PAGE_NR;
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if (qm->ver == QM_HW_V1)
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uacce->api_ver = HISI_QM_API_VER_BASE;
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} else {
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else if (qm->ver == QM_HW_V2)
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uacce->api_ver = HISI_QM_API_VER2_BASE;
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else
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uacce->api_ver = HISI_QM_API_VER3_BASE;
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if (qm->ver == QM_HW_V1)
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mmio_page_nr = QM_DOORBELL_PAGE_NR;
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else if (qm->ver == QM_HW_V2 || !qm->use_db_isolation)
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mmio_page_nr = QM_DOORBELL_PAGE_NR +
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QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
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uacce->api_ver = HISI_QM_API_VER2_BASE;
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}
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else
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mmio_page_nr = qm->db_interval / PAGE_SIZE;
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dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
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sizeof(struct qm_cqe) * QM_Q_DEPTH) >> PAGE_SHIFT;
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@ -2561,13 +2575,23 @@ static void hisi_qm_pre_init(struct hisi_qm *qm)
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qm->misc_ctl = false;
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}
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static void qm_put_pci_res(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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if (qm->use_db_isolation)
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iounmap(qm->db_io_base);
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iounmap(qm->io_base);
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pci_release_mem_regions(pdev);
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}
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static void hisi_qm_pci_uninit(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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pci_free_irq_vectors(pdev);
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iounmap(qm->io_base);
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pci_release_mem_regions(pdev);
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qm_put_pci_res(qm);
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pci_disable_device(pdev);
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}
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@ -4236,6 +4260,67 @@ static int qm_get_qp_num(struct hisi_qm *qm)
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return 0;
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}
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static int qm_get_pci_res(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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int ret;
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ret = pci_request_mem_regions(pdev, qm->dev_name);
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if (ret < 0) {
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dev_err(dev, "Failed to request mem regions!\n");
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return ret;
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}
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qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
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qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
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if (!qm->io_base) {
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ret = -EIO;
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goto err_request_mem_regions;
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}
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if (qm->ver > QM_HW_V2) {
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if (qm->fun_type == QM_HW_PF)
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qm->use_db_isolation = readl(qm->io_base +
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QM_QUE_ISO_EN) & BIT(0);
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else
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qm->use_db_isolation = readl(qm->io_base +
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QM_QUE_ISO_CFG_V) & BIT(0);
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}
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if (qm->use_db_isolation) {
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qm->db_interval = QM_QP_DB_INTERVAL;
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qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4);
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qm->db_io_base = ioremap(qm->db_phys_base,
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pci_resource_len(pdev, PCI_BAR_4));
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if (!qm->db_io_base) {
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ret = -EIO;
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goto err_ioremap;
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}
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} else {
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qm->db_phys_base = qm->phys_base;
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qm->db_io_base = qm->io_base;
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qm->db_interval = 0;
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}
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if (qm->fun_type == QM_HW_PF) {
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ret = qm_get_qp_num(qm);
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if (ret)
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goto err_db_ioremap;
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}
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return 0;
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err_db_ioremap:
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if (qm->use_db_isolation)
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iounmap(qm->db_io_base);
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err_ioremap:
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iounmap(qm->io_base);
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err_request_mem_regions:
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pci_release_mem_regions(pdev);
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return ret;
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}
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static int hisi_qm_pci_init(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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@ -4249,48 +4334,30 @@ static int hisi_qm_pci_init(struct hisi_qm *qm)
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return ret;
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}
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ret = pci_request_mem_regions(pdev, qm->dev_name);
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if (ret < 0) {
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dev_err(dev, "Failed to request mem regions!\n");
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ret = qm_get_pci_res(qm);
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if (ret)
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goto err_disable_pcidev;
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}
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qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
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qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
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qm->io_base = ioremap(qm->phys_base, qm->phys_size);
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if (!qm->io_base) {
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ret = -EIO;
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goto err_release_mem_regions;
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}
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if (qm->fun_type == QM_HW_PF) {
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ret = qm_get_qp_num(qm);
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if (ret)
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goto err_iounmap;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (ret < 0)
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goto err_iounmap;
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goto err_get_pci_res;
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pci_set_master(pdev);
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if (!qm->ops->get_irq_num) {
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ret = -EOPNOTSUPP;
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goto err_iounmap;
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goto err_get_pci_res;
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}
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num_vec = qm->ops->get_irq_num(qm);
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ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
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if (ret < 0) {
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dev_err(dev, "Failed to enable MSI vectors!\n");
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goto err_iounmap;
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goto err_get_pci_res;
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}
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return 0;
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err_iounmap:
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iounmap(qm->io_base);
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err_release_mem_regions:
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pci_release_mem_regions(pdev);
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err_get_pci_res:
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qm_put_pci_res(qm);
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err_disable_pcidev:
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pci_disable_device(pdev);
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return ret;
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@ -4310,28 +4377,28 @@ int hisi_qm_init(struct hisi_qm *qm)
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hisi_qm_pre_init(qm);
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ret = qm_alloc_uacce(qm);
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if (ret < 0)
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dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
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ret = hisi_qm_pci_init(qm);
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if (ret)
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goto err_remove_uacce;
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return ret;
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ret = qm_irq_register(qm);
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if (ret)
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goto err_pci_uninit;
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goto err_pci_init;
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if (qm->fun_type == QM_HW_VF && qm->ver != QM_HW_V1) {
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/* v2 starts to support get vft by mailbox */
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ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
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if (ret)
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goto err_irq_unregister;
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goto err_irq_register;
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}
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ret = qm_alloc_uacce(qm);
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if (ret < 0)
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dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
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ret = hisi_qm_memory_init(qm);
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if (ret)
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goto err_irq_unregister;
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goto err_alloc_uacce;
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INIT_WORK(&qm->work, qm_work_process);
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if (qm->fun_type == QM_HW_PF)
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@ -4341,13 +4408,13 @@ int hisi_qm_init(struct hisi_qm *qm)
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return 0;
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err_irq_unregister:
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qm_irq_unregister(qm);
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err_pci_uninit:
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hisi_qm_pci_uninit(qm);
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err_remove_uacce:
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err_alloc_uacce:
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uacce_remove(qm->uacce);
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qm->uacce = NULL;
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err_irq_register:
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qm_irq_unregister(qm);
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err_pci_init:
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hisi_qm_pci_uninit(qm);
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return ret;
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}
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EXPORT_SYMBOL_GPL(hisi_qm_init);
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@ -202,6 +202,7 @@ struct hisi_qm {
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const char *dev_name;
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struct pci_dev *pdev;
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void __iomem *io_base;
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void __iomem *db_io_base;
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u32 sqe_size;
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u32 qp_base;
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u32 qp_num;
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@ -209,6 +210,7 @@ struct hisi_qm {
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u32 ctrl_qp_num;
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u32 max_qp_num;
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u32 vfs_num;
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u32 db_interval;
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struct list_head list;
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struct hisi_qm_list *qm_list;
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@ -250,7 +252,7 @@ struct hisi_qm {
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/* doorbell isolation enable */
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bool use_db_isolation;
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resource_size_t phys_base;
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resource_size_t phys_size;
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resource_size_t db_phys_base;
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struct uacce_device *uacce;
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int mode;
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};
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@ -16,6 +16,7 @@ struct hisi_qp_ctx {
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#define HISI_QM_API_VER_BASE "hisi_qm_v1"
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#define HISI_QM_API_VER2_BASE "hisi_qm_v2"
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#define HISI_QM_API_VER3_BASE "hisi_qm_v3"
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/* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */
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#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
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