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PCI: Add PTM clock granularity information

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The PTM Control register (PCIe r3.1, sec 7.32.3) contains an Effective
Granularity field:

  This provides information relating to the expected accuracy of the PTM
  clock, but does not otherwise affect the PTM mechanism.

Set the Effective Granularity based on the PTM Root and any intervening PTM
Time Sources.

This does not set Effective Granularity for Root Complex Integrated
Endpoints because I don't know how to figure out clock granularity for
them.  The spec says:

  ... system software must set [Effective Granularity] to the value
  reported in the Local Clock Granularity field by the associated PTM
  Time Source.

but I don't know how to identify the associated PTM Time Source.  Normally
it's the upstream bridge, but an integrated endpoint has no upstream
bridge.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Bjorn Helgaas 2016-06-12 16:26:40 -05:00
parent eec097d431
commit 8b2ec318ee
3 changed files with 31 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/pci/pcie/ptm.c
View File

@ -19,13 +19,29 @@
static void pci_ptm_info(struct pci_dev *dev)
{
dev_info(&dev->dev, "PTM enabled%s\n", dev->ptm_root ? " (root)" : "");
char clock_desc[8];
switch (dev->ptm_granularity) {
case 0:
snprintf(clock_desc, sizeof(clock_desc), "unknown");
break;
case 255:
snprintf(clock_desc, sizeof(clock_desc), ">254ns");
break;
default:
snprintf(clock_desc, sizeof(clock_desc), "%udns",
dev->ptm_granularity);
break;
}
dev_info(&dev->dev, "PTM enabled%s, %s granularity\n",
dev->ptm_root ? " (root)" : "", clock_desc);
}
void pci_ptm_init(struct pci_dev *dev)
{
int pos;
u32 cap, ctrl;
u8 local_clock;
struct pci_dev *ups;
if (!pci_is_pcie(dev))
@ -45,6 +61,7 @@ void pci_ptm_init(struct pci_dev *dev)
return;
pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
/*
* There's no point in enabling PTM unless it's enabled in the
@ -55,14 +72,20 @@ void pci_ptm_init(struct pci_dev *dev)
ups = pci_upstream_bridge(dev);
if (ups && ups->ptm_enabled) {
ctrl = PCI_PTM_CTRL_ENABLE;
if (ups->ptm_granularity == 0)
dev->ptm_granularity = 0;
else if (ups->ptm_granularity > local_clock)
dev->ptm_granularity = ups->ptm_granularity;
} else {
if (cap & PCI_PTM_CAP_ROOT) {
ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
dev->ptm_root = 1;
dev->ptm_granularity = local_clock;
} else
return;
}
ctrl |= dev->ptm_granularity << 8;
pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
dev->ptm_enabled = 1;
@ -98,18 +121,22 @@ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
ups = pci_upstream_bridge(dev);
if (!ups || !ups->ptm_enabled)
return -EINVAL;
dev->ptm_granularity = ups->ptm_granularity;
} else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
dev->ptm_granularity = 0;
} else
return -EINVAL;
ctrl = PCI_PTM_CTRL_ENABLE;
ctrl |= dev->ptm_granularity << 8;
pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
dev->ptm_enabled = 1;
pci_ptm_info(dev);
if (granularity)
*granularity = 0;
*granularity = dev->ptm_granularity;
return 0;
}
EXPORT_SYMBOL(pci_enable_ptm);

1
include/linux/pci.h
View File

@ -371,6 +371,7 @@ struct pci_dev {
#ifdef CONFIG_PCIE_PTM
unsigned int ptm_root:1;
unsigned int ptm_enabled:1;
u8 ptm_granularity;
#endif
#ifdef CONFIG_PCI_MSI
const struct attribute_group **msi_irq_groups;

1
include/uapi/linux/pci_regs.h
View File

@ -969,6 +969,7 @@
#define PCI_PTM_CAP 0x04 /* PTM Capability */
#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
#define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */
#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */
#define PCI_PTM_CTRL 0x08 /* PTM Control */
#define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
#define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */