drm/amdgpu/mes: modify mes api for mmio queue reset

Add me/pipe/queue parameters for queue reset input.

v2: fix build (Alex)

Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiadong Zhu 2024-07-04 12:10:59 +08:00 committed by Alex Deucher
parent 8fe4fde381
commit 8b2429a13f
4 changed files with 17 additions and 4 deletions

View File

@ -873,7 +873,8 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring,
unsigned int vmid)
unsigned int vmid,
bool use_mmio)
{
struct mes_reset_legacy_queue_input queue_input;
int r;

View File

@ -252,6 +252,13 @@ struct mes_remove_queue_input {
struct mes_reset_queue_input {
uint32_t doorbell_offset;
uint64_t gang_context_addr;
bool use_mmio;
uint32_t queue_type;
uint32_t me_id;
uint32_t pipe_id;
uint32_t queue_id;
uint32_t xcc_id;
uint32_t vmid;
};
struct mes_map_legacy_queue_input {
@ -288,6 +295,8 @@ struct mes_resume_gang_input {
struct mes_reset_legacy_queue_input {
uint32_t queue_type;
uint32_t doorbell_offset;
bool use_mmio;
uint32_t me_id;
uint32_t pipe_id;
uint32_t queue_id;
uint64_t mqd_addr;
@ -397,6 +406,8 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
int *queue_id);
int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id);
int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type,
int me_id, int pipe_id, int queue_id, int vmid);
int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring);
@ -406,7 +417,8 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
u64 gpu_addr, u64 seq);
int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
struct amdgpu_ring *ring,
unsigned int vmid);
unsigned int vmid,
bool use_mmio);
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
int amdgpu_mes_wreg(struct amdgpu_device *adev,

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@ -6549,7 +6549,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
struct amdgpu_device *adev = ring->adev;
int r;
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
if (r)
return r;

View File

@ -5163,7 +5163,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
struct amdgpu_device *adev = ring->adev;
int r;
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid);
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
if (r) {
dev_err(adev->dev, "reset via MES failed %d\n", r);
return r;