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drm/bridge: nwl-dsi: Use vsync/hsync polarity from display mode
Using the correct bit helps. The documentation specifies bit 0 in both registers to be controlling polarity of dpi_vsync_input and dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be set. Tested with panel that requires active high vsync and hsync. Signed-off-by: Esben Haabendal <esben@geanix.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240814-nwl-dsi-sync-polarity-v1-1-ee198e369196@geanix.com
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@ -289,13 +289,13 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
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nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
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nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
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/*
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* Adjusting input polarity based on the video mode results in
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* a black screen so always pick active low:
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*/
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nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
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dsi->mode.flags & DRM_MODE_FLAG_PVSYNC ?
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NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH :
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NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
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nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
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dsi->mode.flags & DRM_MODE_FLAG_PHSYNC ?
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NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH :
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NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
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burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
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@ -30,11 +30,11 @@
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#define NWL_DSI_PIXEL_FORMAT 0x20c
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#define NWL_DSI_VSYNC_POLARITY 0x210
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#define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
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#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
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#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(0)
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#define NWL_DSI_HSYNC_POLARITY 0x214
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#define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
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#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
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#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(0)
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#define NWL_DSI_VIDEO_MODE 0x218
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#define NWL_DSI_HFP 0x21c
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