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drm/amdgpu: Simplify amdgpu_lockup_timeout usage.
With introduction of amdgpu_gpu_recovery we don't need any more to rely on amdgpu_lockup_timeout == 0 for disabling GPU reset. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1229,6 +1229,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
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amdgpu_vram_page_split);
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amdgpu_vram_page_split = 1024;
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}
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if (amdgpu_lockup_timeout == 0) {
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dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
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amdgpu_lockup_timeout = 10000;
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}
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}
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/**
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@ -2827,7 +2832,7 @@ bool amdgpu_need_backup(struct amdgpu_device *adev)
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if (adev->flags & AMD_IS_APU)
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return false;
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return amdgpu_lockup_timeout > 0 ? true : false;
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return amdgpu_gpu_recovery;
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}
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static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
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@ -90,7 +90,7 @@ int amdgpu_disp_priority = 0;
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int amdgpu_hw_i2c = 0;
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int amdgpu_pcie_gen2 = -1;
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int amdgpu_msi = -1;
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int amdgpu_lockup_timeout = 0;
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int amdgpu_lockup_timeout = 10000;
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int amdgpu_dpm = -1;
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int amdgpu_fw_load_type = -1;
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int amdgpu_aspm = -1;
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@ -166,7 +166,7 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
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MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(msi, amdgpu_msi, int, 0444);
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
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module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
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MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
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@ -410,7 +410,6 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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unsigned num_hw_submission)
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{
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long timeout;
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int r;
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/* Check that num_hw_submission is a power of two */
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@ -434,20 +433,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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/* No need to setup the GPU scheduler for KIQ ring */
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if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
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timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
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if (timeout == 0) {
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/*
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* FIXME:
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* Delayed workqueue cannot use it directly,
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* so the scheduler will not use delayed workqueue if
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* MAX_SCHEDULE_TIMEOUT is set.
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* Currently keep it simple and silly.
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*/
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timeout = MAX_SCHEDULE_TIMEOUT;
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}
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r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
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num_hw_submission, amdgpu_job_hang_limit,
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timeout, ring->name);
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msecs_to_jiffies(amdgpu_lockup_timeout), ring->name);
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if (r) {
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DRM_ERROR("Failed to create scheduler on ring %s.\n",
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ring->name);
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@ -277,7 +277,7 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
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int r;
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/* trigger gpu-reset by hypervisor only if TDR disbaled */
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if (amdgpu_lockup_timeout == 0) {
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if (!amdgpu_gpu_recovery) {
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/* see what event we get */
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r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
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@ -545,7 +545,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev,
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int r;
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/* trigger gpu-reset by hypervisor only if TDR disbaled */
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if (amdgpu_lockup_timeout == 0) {
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if (!amdgpu_gpu_recovery) {
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/* see what event we get */
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r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
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