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Merge branch 'for-greg' of git://gitorious.org/usb/usb into usb-linus
* 'for-greg' of git://gitorious.org/usb/usb: USB: musb: blackfin: work around anomaly 05000450 usb: musb: Fix the crash issue during reboot usb: musb: gadget: check the correct list_head usb: musb: temporarily make it bool USB: musb: dereferencing an iomem pointer USB: musb: silence printk format warning USB: musb: using 0 instead of NULL USB: musb: add missing unlock in cppi_interrupt() usb: musb: ux500: copy dma mask from platform device to musb device usb: musb: clear AUTOSET while clearing DMAENAB
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commit
86a45a023d
@ -14,7 +14,7 @@ config USB_MUSB_HDRC
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select TWL4030_USB if MACH_OMAP_3430SDP
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select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
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select USB_OTG_UTILS
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tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
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bool 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
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help
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Say Y here if your system has a dual role high speed USB
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controller based on the Mentor Graphics silicon IP. Then
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@ -30,8 +30,8 @@ config USB_MUSB_HDRC
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If you do not know what this is, please say N.
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To compile this driver as a module, choose M here; the
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module will be called "musb-hdrc".
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# To compile this driver as a module, choose M here; the
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# module will be called "musb-hdrc".
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choice
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prompt "Platform Glue Layer"
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@ -21,6 +21,7 @@
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#include <asm/cacheflush.h>
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#include "musb_core.h"
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#include "musbhsdma.h"
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#include "blackfin.h"
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struct bfin_glue {
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@ -332,6 +333,27 @@ static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
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return -EIO;
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}
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static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
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u16 packet_sz, u8 *mode,
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dma_addr_t *dma_addr, u32 *len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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/*
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* Anomaly 05000450 might cause data corruption when using DMA
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* MODE 1 transmits with short packet. So to work around this,
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* we truncate all MODE 1 transfers down to a multiple of the
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* max packet size, and then do the last short packet transfer
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* (if there is any) using MODE 0.
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*/
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if (ANOMALY_05000450) {
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if (musb_channel->transmit && *mode == 1)
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*len = *len - (*len % packet_sz);
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}
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return 0;
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}
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static void bfin_musb_reg_init(struct musb *musb)
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{
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if (ANOMALY_05000346) {
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@ -430,6 +452,8 @@ static const struct musb_platform_ops bfin_ops = {
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.vbus_status = bfin_musb_vbus_status,
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.set_vbus = bfin_musb_set_vbus,
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.adjust_channel_params = bfin_musb_adjust_channel_params,
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};
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static u64 bfin_dmamask = DMA_BIT_MASK(32);
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@ -597,12 +597,12 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
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length = min(n_bds * maxpacket, length);
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}
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DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%x len %u\n",
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DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
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tx->index,
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maxpacket,
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rndis ? "rndis" : "transparent",
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n_bds,
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addr, length);
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(unsigned long long)addr, length);
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cppi_rndis_update(tx, 0, musb->ctrl_base, rndis);
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@ -820,7 +820,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
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length = min(n_bds * maxpacket, length);
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DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
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"dma 0x%x len %u %u/%u\n",
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"dma 0x%llx len %u %u/%u\n",
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rx->index, maxpacket,
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onepacket
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? (is_rndis ? "rndis" : "onepacket")
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@ -829,7 +829,8 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
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musb_readl(tibase,
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DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
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& 0xffff,
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addr, length, rx->channel.actual_len, rx->buf_len);
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(unsigned long long)addr, length,
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rx->channel.actual_len, rx->buf_len);
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/* only queue one segment at a time, since the hardware prevents
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* correct queue shutdown after unexpected short packets
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@ -1039,9 +1040,9 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
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if (!completed && (bd->hw_options & CPPI_OWN_SET))
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break;
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DBG(5, "C/RXBD %08x: nxt %08x buf %08x "
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DBG(5, "C/RXBD %llx: nxt %08x buf %08x "
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"off.len %08x opt.len %08x (%d)\n",
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bd->dma, bd->hw_next, bd->hw_bufp,
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(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
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bd->hw_off_len, bd->hw_options,
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rx->channel.actual_len);
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@ -1111,11 +1112,12 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
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musb_ep_select(cppi->mregs, rx->index + 1);
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csr = musb_readw(regs, MUSB_RXCSR);
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if (csr & MUSB_RXCSR_DMAENAB) {
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DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n",
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DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n",
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rx->index,
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rx->head, rx->tail,
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rx->last_processed
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? rx->last_processed->dma
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? (unsigned long long)
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rx->last_processed->dma
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: 0,
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completed ? ", completed" : "",
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csr);
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@ -1167,8 +1169,11 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
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tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
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rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
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if (!tx && !rx)
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if (!tx && !rx) {
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if (cppi->irq)
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spin_unlock_irqrestore(&musb->lock, flags);
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return IRQ_NONE;
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}
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DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
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@ -1199,7 +1204,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
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*/
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if (NULL == bd) {
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DBG(1, "null BD\n");
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tx_ram->tx_complete = 0;
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musb_writel(&tx_ram->tx_complete, 0, 0);
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continue;
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}
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@ -1452,7 +1457,7 @@ static int cppi_channel_abort(struct dma_channel *channel)
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* compare mode by writing 1 to the tx_complete register.
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*/
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cppi_reset_tx(tx_ram, 1);
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cppi_ch->head = 0;
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cppi_ch->head = NULL;
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musb_writel(&tx_ram->tx_complete, 0, 1);
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cppi_dump_tx(5, cppi_ch, " (done teardown)");
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@ -1030,6 +1030,7 @@ static void musb_shutdown(struct platform_device *pdev)
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struct musb *musb = dev_to_musb(&pdev->dev);
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unsigned long flags;
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pm_runtime_get_sync(musb->controller);
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spin_lock_irqsave(&musb->lock, flags);
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musb_platform_disable(musb);
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musb_generic_disable(musb);
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@ -1040,6 +1041,7 @@ static void musb_shutdown(struct platform_device *pdev)
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_platform_exit(musb);
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pm_runtime_put(musb->controller);
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/* FIXME power down */
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}
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@ -261,6 +261,7 @@ enum musb_g_ep0_state {
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* @try_ilde: tries to idle the IP
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* @vbus_status: returns vbus status if possible
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* @set_vbus: forces vbus status
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* @channel_program: pre check for standard dma channel_program func
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*/
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struct musb_platform_ops {
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int (*init)(struct musb *musb);
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@ -274,6 +275,10 @@ struct musb_platform_ops {
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int (*vbus_status)(struct musb *musb);
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void (*set_vbus)(struct musb *musb, int on);
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int (*adjust_channel_params)(struct dma_channel *channel,
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u16 packet_sz, u8 *mode,
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dma_addr_t *dma_addr, u32 *len);
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};
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/*
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@ -535,7 +535,7 @@ void musb_g_tx(struct musb *musb, u8 epnum)
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is_dma = 1;
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csr |= MUSB_TXCSR_P_WZC_BITS;
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csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
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MUSB_TXCSR_TXPKTRDY);
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MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
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musb_writew(epio, MUSB_TXCSR, csr);
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/* Ensure writebuffer is empty. */
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csr = musb_readw(epio, MUSB_TXCSR);
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@ -1296,7 +1296,7 @@ static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
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}
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/* if the hardware doesn't have the request, easy ... */
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if (musb_ep->req_list.next != &request->list || musb_ep->busy)
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if (musb_ep->req_list.next != &req->list || musb_ep->busy)
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musb_g_giveback(musb_ep, request, -ECONNRESET);
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/* ... else abort the dma transfer ... */
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@ -169,6 +169,14 @@ static int dma_channel_program(struct dma_channel *channel,
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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/* Let targets check/tweak the arguments */
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if (musb->ops->adjust_channel_params) {
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int ret = musb->ops->adjust_channel_params(channel,
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packet_sz, &mode, &dma_addr, &len);
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if (ret)
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return ret;
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}
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/*
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* The DMA engine in RTL1.8 and above cannot handle
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* DMA addresses that are not aligned to a 4 byte boundary.
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}
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musb->dev.parent = &pdev->dev;
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musb->dev.dma_mask = pdev->dev.dma_mask;
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musb->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
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glue->dev = &pdev->dev;
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glue->musb = musb;
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