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pinctrl: cy8c95x0: Use regmap ranges
Instead of implementing a custom register paging mechanism in the driver use the existing regmap ranges feature. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240521152602.1097764-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Patrick Rudolph
Linus Walleij
parent
f71aba339a
commit
8670de9fae
@ -58,9 +58,14 @@
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#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
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#define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE)
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#define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK)
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#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
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#define MAX_BANK 8
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#define BANK_SZ 8
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#define MAX_LINE (MAX_BANK * BANK_SZ)
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#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK)
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#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
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#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1)
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#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
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(CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
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static const struct i2c_device_id cy8c95x0_id[] = {
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{ "cy8c9520", 20, },
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@ -120,18 +125,11 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
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{}
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};
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#define MAX_BANK 8
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#define BANK_SZ 8
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#define MAX_LINE (MAX_BANK * BANK_SZ)
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#define MUXED_STRIDE 16
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#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
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/**
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* struct cy8c95x0_pinctrl - driver data
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* @regmap: Device's regmap. Only direct access registers.
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* @muxed_regmap: Regmap for all muxed registers.
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* @irq_lock: IRQ bus lock
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* @i2c_lock: Mutex for the device internal mux register
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* @i2c_lock: Mutex to hold while using the regmap
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* @irq_mask: I/O bits affected by interrupts
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* @irq_trig_raise: I/O bits affected by raising voltage level
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* @irq_trig_fall: I/O bits affected by falling voltage level
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@ -152,7 +150,6 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
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*/
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struct cy8c95x0_pinctrl {
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struct regmap *regmap;
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struct regmap *muxed_regmap;
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struct mutex irq_lock;
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struct mutex i2c_lock;
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DECLARE_BITMAP(irq_mask, MAX_LINE);
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@ -331,6 +328,9 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
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static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
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{
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if (reg >= CY8C95X0_VIRTUAL)
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return true;
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switch (reg) {
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case 0x24 ... 0x27:
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return false;
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@ -341,6 +341,9 @@ static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
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static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
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{
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if (reg >= CY8C95X0_VIRTUAL)
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return true;
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switch (reg) {
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case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
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return false;
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@ -433,98 +436,21 @@ static bool cy8c95x0_quick_path_register(unsigned int reg)
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}
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}
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static const struct reg_default cy8c95x0_reg_defaults[] = {
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{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
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{ CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
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{ CY8C95X0_PORTSEL, 0 },
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{ CY8C95X0_PWMSEL, 0 },
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static const struct regmap_range_cfg cy8c95x0_ranges[] = {
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{
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.range_min = CY8C95X0_VIRTUAL,
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.range_max = 0, /* Updated at runtime */
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.selector_reg = CY8C95X0_PORTSEL,
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.selector_mask = 0x07,
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.selector_shift = 0x0,
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.window_start = CY8C95X0_INTMASK,
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.window_len = MUXED_STRIDE,
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}
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};
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static int
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cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val)
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{
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struct cy8c95x0_pinctrl *chip = context;
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u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
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int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
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/* Select the correct bank */
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ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
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if (ret < 0)
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goto out;
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/*
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* Read the register through direct access regmap. The target range
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* is marked volatile.
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*/
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return regmap_read(chip->regmap, reg, val);
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}
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static int
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cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val)
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{
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struct cy8c95x0_pinctrl *chip = context;
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u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
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int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
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/* Select the correct bank */
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ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
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if (ret < 0)
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goto out;
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/*
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* Write the register through direct access regmap. The target range
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* is marked volatile.
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*/
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return regmap_write(chip->regmap, reg, val);
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}
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static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(i2c);
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u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
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u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
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if (port >= chip->nport)
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return false;
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return cy8c95x0_muxed_register(reg);
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}
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static struct regmap_bus cy8c95x0_regmap_bus = {
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.reg_read = cy8c95x0_mux_reg_read,
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.reg_write = cy8c95x0_mux_reg_write,
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};
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/* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */
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static const struct regmap_config cy8c95x0_muxed_regmap = {
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.name = "muxed",
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static const struct regmap_config cy8c9520_i2c_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_FLAT,
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.use_single_read = true,
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.use_single_write = true,
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.max_register = MUXED_STRIDE * BANK_SZ,
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.num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
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.readable_reg = cy8c95x0_mux_accessible_register,
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.writeable_reg = cy8c95x0_mux_accessible_register,
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.disable_locking = true,
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};
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/* Direct access regmap */
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static const struct regmap_config cy8c95x0_i2c_regmap = {
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.name = "direct",
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.reg_bits = 8,
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.val_bits = 8,
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.reg_defaults = cy8c95x0_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
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.readable_reg = cy8c95x0_readable_register,
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.writeable_reg = cy8c95x0_writeable_register,
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@ -532,7 +458,11 @@ static const struct regmap_config cy8c95x0_i2c_regmap = {
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.precious_reg = cy8c95x0_precious_register,
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.cache_type = REGCACHE_FLAT,
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.max_register = CY8C95X0_COMMAND,
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.ranges = NULL, /* Updated at runtime */
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.num_ranges = 1,
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.max_register = 0, /* Updated at runtime */
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.num_reg_defaults_raw = 0, /* Updated at runtime */
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.use_single_read = true, /* Workaround for regcache bug */
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.disable_locking = true,
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};
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@ -544,7 +474,6 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip
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bool *change, bool async,
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bool force)
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{
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struct regmap *regmap;
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int ret, off, i, read_val;
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/* Caller should never modify PORTSEL directly */
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@ -553,12 +482,10 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip
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mutex_lock(&chip->i2c_lock);
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/* Registers behind the PORTSEL mux have their own regmap */
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/* Registers behind the PORTSEL mux have their own range in regmap */
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if (cy8c95x0_muxed_register(reg)) {
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regmap = chip->muxed_regmap;
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off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
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} else {
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regmap = chip->regmap;
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/* Quick path direct access registers honor the port argument */
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if (cy8c95x0_quick_path_register(reg))
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off = reg + port;
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@ -566,7 +493,7 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip
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off = reg;
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}
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ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
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ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
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if (ret < 0)
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goto out;
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@ -577,16 +504,16 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip
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continue;
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off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
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ret = regmap_read(regmap, off, &read_val);
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ret = regmap_read(chip->regmap, off, &read_val);
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if (ret < 0)
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continue;
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if (!(read_val & mask & val))
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continue;
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regcache_cache_only(regmap, true);
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regmap_update_bits(regmap, off, mask & val, 0);
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regcache_cache_only(regmap, false);
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regcache_cache_only(chip->regmap, true);
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regmap_update_bits(chip->regmap, off, mask & val, 0);
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regcache_cache_only(chip->regmap, false);
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}
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}
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out:
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@ -662,17 +589,14 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i
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static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
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unsigned int port, unsigned int *read_val)
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{
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struct regmap *regmap;
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int off, ret;
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mutex_lock(&chip->i2c_lock);
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/* Registers behind the PORTSEL mux have their own regmap */
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/* Registers behind the PORTSEL mux have their own range in regmap */
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if (cy8c95x0_muxed_register(reg)) {
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regmap = chip->muxed_regmap;
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off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
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} else {
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regmap = chip->regmap;
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/* Quick path direct access registers honor the port argument */
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if (cy8c95x0_quick_path_register(reg))
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off = reg + port;
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@ -680,7 +604,7 @@ static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
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off = reg;
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}
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ret = regmap_read(regmap, off, read_val);
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ret = regmap_read(chip->regmap, off, read_val);
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mutex_unlock(&chip->i2c_lock);
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@ -1513,6 +1437,8 @@ static int cy8c95x0_detect(struct i2c_client *client,
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static int cy8c95x0_probe(struct i2c_client *client)
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{
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struct cy8c95x0_pinctrl *chip;
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struct regmap_config regmap_conf;
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struct regmap_range_cfg regmap_range_conf;
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struct regulator *reg;
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int ret;
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@ -1532,15 +1458,20 @@ static int cy8c95x0_probe(struct i2c_client *client)
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chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
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chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
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memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
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switch (chip->tpin) {
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case 20:
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strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
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regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
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break;
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case 40:
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strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
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regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
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break;
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case 60:
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strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
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regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
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break;
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default:
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return -ENODEV;
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@ -1573,22 +1504,18 @@ static int cy8c95x0_probe(struct i2c_client *client)
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gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
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}
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/* Generic regmap for direct access registers */
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chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
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/* Regmap for direct and paged registers */
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memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
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regmap_conf.ranges = ®map_range_conf;
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regmap_conf.max_register = regmap_range_conf.range_max;
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regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
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chip->regmap = devm_regmap_init_i2c(client, ®map_conf);
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if (IS_ERR(chip->regmap)) {
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ret = PTR_ERR(chip->regmap);
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goto err_exit;
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}
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/* Port specific regmap behind PORTSEL mux */
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chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus,
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chip, &cy8c95x0_muxed_regmap);
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if (IS_ERR(chip->muxed_regmap)) {
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ret = dev_err_probe(&client->dev, PTR_ERR(chip->muxed_regmap),
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"Failed to register muxed regmap\n");
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goto err_exit;
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}
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bitmap_zero(chip->push_pull, MAX_LINE);
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bitmap_zero(chip->shiftmask, MAX_LINE);
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bitmap_set(chip->shiftmask, 0, 20);
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