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oprofile/x86: return -EBUSY if counters are already reserved
In case a counter is already reserved by the watchdog or perf_event subsystem, oprofile ignored this counters silently. This case is handled now and oprofile_setup() now reports an error. Signed-off-by: Robert Richter <robert.richter@amd.com>
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83300ce0df
commit
8617f98c00
@ -357,7 +357,10 @@ static int nmi_setup(void)
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*/
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/* Assume saved/restored counters are the same on all CPUs */
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model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
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err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
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if (err)
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goto fail;
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for_each_possible_cpu(cpu) {
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if (!cpu)
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continue;
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@ -138,21 +138,30 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
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}
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}
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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continue;
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goto fail;
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if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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continue;
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goto fail;
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}
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/* both registers must be reserved */
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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op_amd_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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@ -172,15 +181,8 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* clear all counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (unlikely(!msrs->controls[i].addr)) {
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if (counter_config[i].enabled && !smp_processor_id())
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/*
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* counter is reserved, this is on all
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* cpus, so report only for cpu #0
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*/
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op_x86_warn_reserved(i);
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if (!msrs->controls[i].addr)
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continue;
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}
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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op_x86_warn_in_use(i);
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@ -404,7 +404,7 @@ static void p4_shutdown(struct op_msrs const * const msrs)
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}
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}
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static void p4_fill_in_addresses(struct op_msrs * const msrs)
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static int p4_fill_in_addresses(struct op_msrs * const msrs)
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{
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unsigned int i;
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unsigned int addr, cccraddr, stag;
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@ -486,6 +486,18 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
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msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
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}
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}
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for (i = 0; i < num_counters; ++i) {
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if (!counter_config[i].enabled)
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continue;
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if (msrs->controls[i].addr)
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continue;
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op_x86_warn_reserved(i);
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p4_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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@ -46,21 +46,30 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
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}
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}
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static void ppro_fill_in_addresses(struct op_msrs * const msrs)
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static int ppro_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < num_counters; i++) {
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if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
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continue;
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goto fail;
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if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
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continue;
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goto fail;
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}
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/* both registers must be reserved */
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msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
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msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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ppro_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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@ -96,15 +105,8 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
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/* clear all counters */
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for (i = 0; i < num_counters; ++i) {
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if (unlikely(!msrs->controls[i].addr)) {
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if (counter_config[i].enabled && !smp_processor_id())
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/*
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* counter is reserved, this is on all
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* cpus, so report only for cpu #0
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*/
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op_x86_warn_reserved(i);
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if (!msrs->controls[i].addr)
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continue;
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}
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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op_x86_warn_in_use(i);
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@ -41,7 +41,7 @@ struct op_x86_model_spec {
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u16 event_mask;
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int (*init)(struct oprofile_operations *ops);
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void (*exit)(void);
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void (*fill_in_addresses)(struct op_msrs * const msrs);
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int (*fill_in_addresses)(struct op_msrs * const msrs);
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void (*setup_ctrs)(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs);
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int (*check_ctrs)(struct pt_regs * const regs,
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