diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt deleted file mode 100644 index 524c3dc5d808..000000000000 --- a/Documentation/devicetree/bindings/arm/insignal-boards.txt +++ /dev/null @@ -1,8 +0,0 @@ -* Insignal's Exynos4210 based Origen evaluation board - -Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC. - -Required root node properties: - - compatible = should be one or more of the following. - (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. - (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index bdadc3da9556..ff75bf7ac3a2 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -1,7 +1,10 @@ -* Samsung's Exynos SoC based boards +* Samsung's Exynos and S5P SoC based boards Required root node properties: - compatible = should be one or more of the following. + - "samsung,aries" - for S5PV210-based Samsung Aries board. + - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board. + - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board. - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - "samsung,monk" - for Exynos3250-based Samsung Simband board. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index be2a489abb8f..9725033c3a55 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -860,6 +860,8 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \ s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ + s5pv210-galaxys.dtb \ s5pv210-goni.dtb \ s5pv210-smdkc110.dtb \ s5pv210-smdkv210.dtb \ diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 962af97c1883..27a1ee28c3bb 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -78,6 +78,22 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; }; }; @@ -226,7 +242,7 @@ interrupts = ; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index dfe41b698745..6085e92ac2d7 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -735,7 +735,7 @@ reg = <0x100C0000 0x100>; interrupts = <2 4>; status = "disabled"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; jpeg_codec: jpeg-codec@11840000 { diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 88fb47cef9a8..b6091c27f155 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -55,6 +55,19 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x901>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi deleted file mode 100644 index 489b58c619ee..000000000000 --- a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4412 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7b43c10c510b..51f72f0327e5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -49,21 +49,30 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2daf505b3d08..da163a40af15 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -84,6 +84,29 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1700000000>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; @@ -278,7 +301,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sata: sata@122f0000 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 20e789ea136f..57fc9c949e54 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -93,7 +93,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -102,7 +102,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -111,7 +111,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -120,7 +120,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; mmc_0: mmc@12200000 { diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index a8e449471304..0ee6e92a3c29 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -38,6 +38,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -49,6 +50,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -60,6 +62,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -83,6 +86,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -94,6 +98,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -105,6 +110,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi deleted file mode 100644 index fbc77cb58473..000000000000 --- a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5420 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * Copyright (c) 2017 Krzysztof Kozlowski - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <0>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index f4e8c5823bc2..aaff15880761 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -738,7 +738,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -747,7 +747,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -756,7 +756,7 @@ interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -765,7 +765,7 @@ interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_gpu: tmu@100a0000 { @@ -774,7 +774,7 @@ interrupts = ; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sysmmu_g2dr: sysmmu@10a60000 { diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 7c130a00d1a8..e4a5857c135f 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -37,6 +37,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -48,6 +49,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -59,6 +61,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -69,8 +72,8 @@ cpu4: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; - clocks = <&clock CLK_ARM_CLK>; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -82,6 +85,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -93,6 +97,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -104,6 +109,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi new file mode 100644 index 000000000000..575094ea7024 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 based Galaxy Aries board device tree source + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + compatible = "samsung,aries", "samsung,s5pv210"; + + aliases { + i2c6 = &i2c_pmic; + i2c9 = &i2c_fuel; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000 + 0x40000000 0x10000000 + 0x50000000 0x08000000>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_gpio_rst>; + post-power-on-delay-ms = <500>; + power-off-delay-us = <500>; + }; + + i2c_pmic: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max8998"; + reg = <0x66>; + interrupt-parent = <&gph0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + max8998,pmic-buck1-default-dvs-idx = <1>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, + <1050000>, <950000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3600000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VGA_VDDIO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VGA_DVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_ISP_HOST_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VGA_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "vddarm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1250000>; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vddint"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + }; + }; + }; + }; + + i2c_fuel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuelgauge@36 { + compatible = "maxim,max17040"; + interrupt-parent = <&vic0>; + interrupts = <7>; + reg = <0x36>; + }; + }; +}; + +&fimd { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_clk &lcd_data24>; + status = "okay"; + + samsung,invert-vden; + samsung,invert-vclk; + + display-timings { + timing-0 { + /* 480x800@60Hz */ + clock-frequency = <25628040>; + hactive = <480>; + vactive = <800>; + hfront-porch = <16>; + hback-porch = <16>; + hsync-len = <2>; + vfront-porch = <28>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; +}; + +&hsotg { + vusb_a-supply = <&ldo8_reg>; + vusb_d-supply = <&ldo3_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&pinctrl0 { + wlan_bt_en: wlan-bt-en { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + wlan_gpio_rst: wlan-gpio-rst { + samsung,pins = "gpg1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_host_wake: wifi-host-wake { + samsung,pins = "gph2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tf_detect: tf-detect { + samsung,pins = "gph3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wifi_wake: wifi-wake { + samsung,pins = "gph3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&sdhci1 { + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <38400000>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; + pinctrl-names = "default"; + cap-sd-highspeed; + cap-mmc-highspeed; + + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gph2>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; + vbus-supply = <&safe1_sreg>; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts new file mode 100644 index 000000000000..ccf761b1babf --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; + compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts new file mode 100644 index 000000000000..842276749717 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; + compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + nand_pwrseq: nand-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&massmemory_en>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "home"; + gpios = <&gph3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&pinctrl0 { + massmemory_en: massmemory-en { + samsung,pins = "gpj2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + mmc-pwrseq = <&nand_pwrseq>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 3a79feab11c3..7f0c9d447871 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -258,6 +258,8 @@ gph2: gph2 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; #interrupt-cells = <2>; };